What are some techniques for filtering and amplifying pulse signals?

[petterg]

1) 1.5mV is the lowest expected pulse. Signal is a little bit weakened by C1. At some point I increased C1 from 30nF to 50nF. Then the resulting amplitude was closer to 1,5mV.
2) Where do you see that?
(Ni Multisim did quite a bit of things that didn't make sense to me)

 

[jim hardy]

2) Where do you see that?

On your oscilloscope screenshot, the red trace that looks flat between negative going pulses.

The ~half millivolt level between pulses is within LM324's input offset(2mv max, 1mv typical) and could be zeroed out.

 

[petterg]

The half mV is for the weakest signal only. Strongest signal is 300 times larger (both drifting offset and pulse). A dynamic way to zero it out would solve the problem perfectly.
I recreated the highpass circuit in LT spice, with the same result as Multisim. I've tested both weak and strong signals. The "flat" area between pulses after the buffer (U1B) seems to start climbing towards the pulse. When the pulse comes almost 5% of the pulse amplitude has already been a part of the almost flat area between the pulses.

In this digital world I'd believe pulse signal would be quite common. How come google gives med nothing about applying filter to pulse signals?

 

[meBigGuy]

Search for impulse response and step response to see what filters do to pulses.

I think you are done if you implement my short pulse detector. Is there a problem with that? 2 comparators and 4 one shots and some logic.

Maybe it's time to think about an AGC. The AD8336 is a variable gain amplifier (there are others). Here is an app note: http://www.analog.com/static/imported-files/application_notes/AN_934.pdf that shows one implementation.

Here is an application note that talks about the gain control implementation in a TI CODEC chip. : http://www.ti.com/lit/an/snaa028a/snaa028a.pdf It's more of an example of AGC in a general way, although it would provide a nice digital ADC interface.

Do a search for varaible gain amplifier IC and there are a slew of them. You can build a detector that outputs a voltage based on the peak levels and use it to control gain. You just need to decide on the attack and decay times.

See http://www.ti.com/lit/ds/sbos395c/sbos395c.pdf

 

[petterg]

I'm having an issue with the 555's. The issue is that the timer starts when trigger goes low, even when reset is low. The result is that if reset goes high before the time runs out, the output goes high. Then problem also occurs if reset is high while trigger goes low, then when reset goes low output goes low, but if reset goes high before the timeout initiated by the trigger before reset, the output will again go high until timeout.

Is there a way to make reset include the discharge and not allow retrigger until next trigger edge?
With that issues solved, I think the oneshot approach will work.

Edit:
Alternatively the timer needs to be retriggered as long as the trigger input is lower than trigger threshold.

Reason is that pulse width may be long when input is strong, and timeout that is more than 50% of a cycle may cause other problems. Timer at 130-140us will work when cycle is exact 200us. Anything outside those 10us will fail. As this is supposed to work in the real world I have to account for some variance. A timer window of 10us is to small. By solving the retrigger, or reset including discharge (or preferably both) the timerrange may be in the range 70-140us. That will be a lot safer.

 

[meBigGuy]

Try a 74121 or 74123 style one shot.

The 555 is hard to use that way.

 

[jim hardy]

Your description of 555 behavior doesn't sound right. Is this a real one or a simulated one?

Tie RESET high.
Make sure you have bypass capacitors across supply, and on CTRL pin.

Tie TRIG and THRESH together, call them INPUT.
Check that it works like a simple inverter: INPUT LOW = Out(and Discharge) HIGH

 

[petterg]

I read about 74121 and 74123. If I got it right, they retrigger on new trigger edge only, they don't retrigger (continuously trigger) while the input is held at trigger level?

How long does the reset need to be held to make sure it reminds in reset state after reset signal is released? I can't find any such information in the documentation.

 

[petterg]

Your description of 555 behavior doesn't sound right. Is this a real one or a simulated one?

Tie RESET high.
Make sure you have bypass capacitors across supply, and on CTRL pin.

Tie TRIG and THRESH together, call them INPUT.
Check that it works like a simple inverter: INPUT LOW = Out(and Discharge) HIGH

It's simulation. I'm not building any real circuit before I've got it working in simulation. Datasheet doesn't say anything about how long the reset must be held low to reset. Simulation indicates that it must be held for whatever time is left of the timeout.

Simulation with TRG connected to THR behaves like you say. Also, if INPUT is low, output follows RST.
Problem is (I think) that DIS doesn't lead any current as long as TRG is low, no matter the position
of RST. To make it work there would need to be some sort of external discharge that is triggered when RST goes low. A transistor to short the timing capacitor has some effect, but it doesn't fully discharge. The other option would be a circuit to rapidly charge the capacitor (above THR) when RST is low.

 

[meBigGuy]

123, 423, etc are retriggerable if that's what you want.

The reset pulse leaves it reset until the next active edge. The spec is right there. 5ns for a 123.
https://www.fairchildsemi.com/ds/74/74VHC123A.pdf

Search for retriggerable monostable or just monostable. There are a ton of parts.

They are mostly edge triggered, as opposed to level triggered. SO, after a reset you need an active edge to trigger again.

 

[jim hardy]

How long does the reset need to be held...

a microsecond should be more than enough

Delay time reset to output is 0.47μs typical. Minimum reset pulse width must be 0.3μs, typical.

http://www.ti.com/lit/ds/symlink/lm555.pdf page 12

 

[NascentOxygen]

I don't know whether this is relevant here, but I'll mention it. When the topic of 555s comes up, I point out that not all 555s behave the same. So long as you stay within the documented uses and the configurations in the application notes, there is no observed difference. But if you start changing things, inventing new arrangements for trigger & threshold, the differences between manufacturers can become apparent.

 

[petterg]

I found this notice in the datasheet for NE555
http://pdf1.alldatasheet.com/datash...3_85UORlHDyRHOIpa/1XXyxeocTlLM+/datasheet.pdf

Applying a negative pulse simultaneously
to the reset terminal (pin 4) and the trigger terminal
(pin 2) during the timing cycle discharges the externalcapacitorand
causes the cycle to start over.The
timing cycle now starts on the positive edge of the
reset pulse.

That is exactly what I experience. All thou it could be written more precise, that the timing cycle starts on negative edge of trigger, so what the notice say occur if reset is released before timeout. And it doesn't matter if the reset and trigger pulses come at the same time or with some delay. While reset is low output is low. While reset is high, output will be high within the timing period. If there is a negative pulse to reset fully within the timing period the output will go low while reset is low, and return to high after the reset pulse. Timing period will start on negative edge og trigger even while reset is low.

Is that behavior unique for NE555 as I don't see anything similar in lm555 datasheet.

Buying a lm555 that is not a ne555 may be a challenge...

 

[petterg]

123, 423, etc are retriggerable if that's what you want.

The reset pulse leaves it reset until the next active edge. The spec is right there. 5ns for a 123.
https://www.fairchildsemi.com/ds/74/74VHC123A.pdf

Search for retriggerable monostable or just monostable. There are a ton of parts.

They are mostly edge triggered, as opposed to level triggered. SO, after a reset you need an active edge to trigger again.

I kind of need level triggered. Or edge triggered output, level retriggered timer.
As I don't see anything similar to the notice quoted above, I can assume that behavior does not apply to 74123?

 

[petterg]

I kind of have a solution now. I'm sure it won't work in a real circuit thou. The chain of components is: buffer - gain x20 - gain x20 - gain x20 - differentiator - low pass filter - gain x10 / inverting gain x11 - 2x 555 - 2x 555.
What makes this work is that I amplify in several steps to keep the wave form better, and I amplify so much that clipping will occur even for the weakest signal. That made the needed timing for the 555's more stable.

The reason this will not work in a real circuit is that all the amplifications will cause even the tiniest noise to trigger the 555's.

 

[jim hardy]

...I amplify so much that clipping will occur even for the weakest signal...

That's a good technique. It is not uncommon to use two diodes in parallel, opposite directions for a feedback 'resistor' around an inverting opamp. That way you don't saturate the amplifier.
Plain diodes give you a ~ 1/2 volt signal, zeners give whatever you want and it can be made asymmetric that way..


It WILL work in real world. All you need do is remove high frequency noise and that low frequency bias before handing signal to clipper.

 

[meBigGuy]

The problem is if there is any inband noise (he has amplified so much the low signal is clipped). I think clipping before low pass filtering is a mistake. I think not using a comparator to feed the logic is also a mistake. But, that's just my opinion. It's easy to sit here and take pot shots.

 

[jim hardy]

Yes, wash the signal of noise then process it.

 

[petterg]

I got too optimistic. Positive pulses when offset is positive, and signal is strong, causes permanent high output form the amplifier. (Opposite when both are negative and strong.) Back to the same unsolved problems...

 

[meBigGuy]

Maybe it's time to think about an AGC. The AD8336 is a variable gain amplifier (there are others). Here is an app note: http://www.analog.com/static/imported-files/application_notes/AN_934.pdf that shows one implementation.

Here is an application note that talks about the gain control implementation in a TI CODEC chip. : http://www.ti.com/lit/an/snaa028a/snaa028a.pdf It's more of an example of AGC in a general way, although it would provide a nice digital ADC interface.

Do a search for varaible gain amplifier IC and there are a slew of them. You can build a detector that outputs a voltage based on the peak levels and use it to control gain. You just need to decide on the attack and decay times.

See http://www.ti.com/lit/ds/sbos395c/sbos395c.pdf

Repost

 

[petterg]

AGC is too complex. Using the IC's in the sample circuit will cost $230 for 4 circuits. A MPU with 4 analog inputs will cost $10. I'd rather go with the MPU then.

I would have gone the MPU-way long time ago, it's just that I can't believe that removing something that is so close to a dc cold be this hard.

I would guess signals in wifi, gsm and other digital wireless communication also would need to filter pulse signals. How is it solved there?

 

[meBigGuy]

Whatever. A VCA820 is $6. And figure 83 shows an implementation with 2 opamps. I'm not sure why you think this is about "filtering pulse signals". It isn't. It's about a high pass filter, proper gain control, and a window comparator.

As for an MPU
You will need somthing like a 14 bit converter and need to consider the cpu cycles needed to implement your processing. I'd recommend high pass filtering before the adc. I'd implement it in C or MATLAB or something first so I could determine the processing requirements and what amount of analog pre-processing I needed before buying a processor. Make sure your sample rate is enough to get 4 or 5 samples per pulse.

Digital wireless uses A/D converters and dedicated dsp processing. They also have analog AGC and analog I/F filtering.

 

[petterg]

I calculated AGC cost for the sample at analog.com. It didn't hit me that TI would be that much cheaper.

I think the MPU code will be simpler than most digital filtering as all it needs to do is to keep track of pulse direction. Basically it must keep track of median voltage for the last 50(?)ms and the average voltage for the last 20us. If the short average is significantly higher than the median there is a positive pulse. If it's significantly lower there's a negative pulse. If no pulse is registered for the last 5ms, signal is lost.
Input must be amplified so that max expected offset is in the range +/-1.7V. That would make the strongest pulse +/-8.5V (clipping to 2.5V) and weakest +/-0.017V. That makes 1024 levels (10bit) for +/-2.5V sufficient.

Anyhow, I got home last night and woke up with a clear mind, which resulted in a retriggerable 555 circuit which seems to work. That makes the differentiator approach come back to life. "Seems" because I can't test it with the rest of the circuit. Turns out that LT spice fail to simulate 2x555 + 6 opamps. 6 opamps + 1 555 = OK. 4 opamps + 2 555 = OK. Once there is one device too much in the sketch - it doesn't even need to be connected to any signal, or the 555's trigger can be connected to V+, the simulation goes on for ever.

 

[meBigGuy]

There are lots of agc methods, variable amplifier chips and ways to skin that cat. All receivers have AGC. All decoders normalize amplitudes to some extent. I just looked for a few minutes and found the TI chip. It is way more high performance that what you need (150MHz if I remember correctly). There are probably cheaper solutions also.

As for your MPU solution, you can do the same thing by filtering for a comparator reference level (a window comparator). As I said, " It's about a high pass filter, proper gain control, and a window comparator."

 

[jim hardy]

You seem to take bigger mental steps than I do. (That's my weakness, not yours)

I would have to get my filters working individually with just resistors and capacitors before adding the opamps.

Opamps let's you cascade them without worry about one loading down the one before it.
But the corner frequencies of your individual filters will clean up the hf noise and block the lf, then you can differentiate and limit. You can get those working one at a time to produce desired function without complication of opamps.

Reason I suggest this is I don't understand your DC offsets. Resistors and capacitors don't tend to add offsets.
When you have found frequencies that work you can sharpen slopes by sallen-key or multiple feedback opamp filter topology.

This should be simple - bandpass, differentiate, limit(clip), count.

But I am probably days behind you.

General rule - when things look confusing, back up and simplify them

good luck and keep on experimenting.

old jim

 

[meBigGuy]

The problem with differentiation in this problem is that it detects both edges, doesn't it? I never got the need for that part of the solution. Seems like it just creates noise. A positive pulse has positive and negative edges. A negative pulse has positive and negative edges. What am I missing?

 

[petterg]

The problem with differentiation in this problem is that it detects both edges, doesn't it? I never got the need for that part of the solution. Seems like it just creates noise. A positive pulse has positive and negative edges. A negative pulse has positive and negative edges. What am I missing?

A positive pulse give a negative pulse, then positive pulse from the differentiator. A negative pulse turns the result the other way around. Thats perfect for triggering a pair of oneshots, one triggered on negative, one triggered on positive, and make sure output from one block the trigger of the other. Hence if the negative pulse comes first, only the negative triggered oneshot will be triggered. I've solved this by having output from one pull the reset on the other. While writing this I realized it would probably be better to stop the trigger signal before it reaches the oneshot input - in particular after I got the retrigger working.

 

[petterg]

You seem to take bigger mental steps than I do. (That's my weakness, not yours)

I would have to get my filters working individually with just resistors and capacitors before adding the opamps.

I'm thinking filters are dependent on the resistance to ground. Hence dependent on the load. The difference between us is that I have no clue what I'm doing. (You have some clue of what I'm doing.) I'll try your way...
[/QUOTE]

 

[petterg]

There are lots of agc methods, variable amplifier chips and ways to skin that cat. All receivers have AGC. All decoders normalize amplitudes to some extent. I just looked for a few minutes and found the TI chip. It is way more high performance that what you need (150MHz if I remember correctly). There are probably cheaper solutions also.

As for your MPU solution, you can do the same thing by filtering for a comparator reference level (a window comparator). As I said, " It's about a high pass filter, proper gain control, and a window comparator."

Use of a comparator requires high pass and gain control to work perfectly. Highpass has not been working so far. I'll give high pass another try.
Comparator would also work if Vref could be dynamic set to the level between pulses = lowpass. But even low pass has not worked out yet. (Thats the idea described in the initial post.)

 

[jim hardy]

The problem with differentiation in this problem is that it detects both edges, doesn't it? I never got the need for that part of the solution. Seems like it just creates noise. A positive pulse has positive and negative edges. A negative pulse has positive and negative edges. What am I missing?

My thought was this:

Thought experiment-
Amplify, filter and limit(clip).
Differentiate.
Ignore negative edges.
Immediately after a positive edge, look at the level of the clipped signal incoming to differentiator.
If that signal is high, then this pulse is a positive one that hasn't expired yet.
If that signal is low, then that pulse was a negative one that has just expired.

Might an edge triggered D flip-flop with clipped pulse for data and differentiated one for clock do it ?

It's immaterial which edge you use, the key is what follows an edge of given direction(up or down) tells you whether the transition was toward or away from zero.
Draw it out on a napkin.

jim