Guidence needed for this circuit

[rama1001]

Hi,
can anyone explain the function of componets in attached diagram. The 2sk170 JFET was named as J1 and AD817 op-amp is used.


input parameters from function generator
----------------------------------------
freq-100Hz
amp-111mv
duty cycle-50%
time-5ms

expected output range is 40mv-100mv and we got that result but confused regarding working function of jfet. Better if it is explained about whole circuit.

 

[yungman]

As I said before, it is a trans-impedance amp. Whith the trans-impedance gain of Rf. The designer want to minimize input leakage/bias current by using a J-FET as input. The FET invert the signal, that is the reason it drive the +ve input of the op-amp. The output drive Rf back to the input.

This circuit is nothing more than something like an inverted gain op-amp circuit. As I told you, for the speed you want, you can use any J-FET input op-amp and be done with it. Cheap J-FET input op-amp like TLO81 will be more than good enough for this purpose. You are limited to about 100 Hz only. Form the last circuit, there is a big 100pF from input to ground, that show already there is not high speed requirement. In the last circuit, the Rf is only 1M which meant the trans-impedance gain is very low! There is nothing that is pushing the technology here.

This is the circuit with single J-FET input op-amp. I put a 50 ohm resistor to separate the parasitic capacitance of the detector from the input of the amp to guarente stability. Rf is the same as in your circuit. You should use +/-6V or higher as supply. Cf can be adjusted to get the frequency response you want.

You cannot test these amps but driving directly from the signal generator, this is common mistake when people work on trans-impedance amps. If you drive directly from the output gain would be very high because the output impedance of the generator is 50 ohm. YOu , it will give you gain of Rf/50 in your circuit or Rf/(50+50) in my circuit. Trans-impedance means you put current in and get voltage out. In your case, you expect about 100mV out, if you consider Rf is 1M, then meaning the max input current is I=0.1V/1M = 100nA. So you put a resistor of 10M from the generator to the input and set the generator to vary from 0 to 1V to get your input requirement.

The key to testing a trans-impedance amp is to use resistor to turn the voltage into current before driving into the amp. The 50 ohm I put in series with the input with separate the input capacitance from the detector diode ( most photo detectors are diodes type) to guarante stability of the trans-impedance amp.

 

[rama1001]

Though your explain clearly but i did not understand correctly due to because of poor knowledge of analog circuits. Any way even my instructor was almost explained in the same way what your trying to me. But one point i remember that the feed-back(Rf and Cf) will help to put some negative voltage (may be -2 or -20 ) on jfet input and some thing like that which exactly i forgotten that concept. But any i have to explain these circuit in my presentations but i am still UN-clear.

How we can say directly by seeing any circuit like what you said "Form the last circuit, there is a big 100pF from input to ground, that show already there is not high speed requirement."

can you push me towards to gain tips like how your analyzing circuits means getting the exact knowledge about how to analyze any kind of circuits.

can still is it possible to explain in much clear way. Please do it for me.

Thank you, Sir.

 

[yungman]

I wish I knew that's what you are looking for, the explanation rather than a workiing circuit! I have people coming over in an hour and I cannot really get to the detail until later tonight or tomorrow.

Go on the web and look for explanation of how op-amp work in inverted gain mode like what I drawn out. Basically op-amp in inverted gain mode is really a trans-impedance amplify. The input resistor in my drawing is just to turn the input voltage into current.

The definition of an op-amp is that it only amplifier the differential voltage between the +ve and -ve input. The op-amp has very high gain at low frequency and the input impedance is very high so no current flow in and out. This is the most important thing to understand before you go any further.

Basically when you inject a current into the -ve input junction of my drawing, before the op-amp can react, the output is still sitting at 0V. so the current will create a +ve voltage at the -ve input from flowing through the Rf. This +ve voltage will cause the output of the amp to swing -ve. It will continue to swing until it take all the current off the -ve input junction so the voltage is zero again. eg, if you put 10EE-6 A of current into the junction, the output of the op-amp will keep swinging -ve until all the 10EE-6A get pulled out through the Rf. To do that, the output has to settle at -1V. Then everything is balance. This is how the inverted op-amp configuration work.

Read articles on this, they can explain better than I can. Other's can come in and explain this too. Keep asking question, and if needed, I'll come back late tonight or tomorrow.

 

[rama1001]

only one straight forward clarification that what JFET(2sk170) is doing over there and how can i describe that...

 

[yungman]

J-FET have very high input impedance. The designer "think" that this would make a difference. For 100nA full scale, you don't need J-FET. I design F-cup amp that detect 10EE-14A, we use special femto amp amplifier to do the design. In your case, even a good bi-polar input op-amp like OP-97 is plenty good. I don't know of any other way but to say...the person that design the circuit don't know what he is doing...Sorry! You gave the input requirement and the Rf=1M. That is just ordinary. We had to worry about the input went our Rf=1G ohm...that is 10EE12 ohms and beyond. Then we really have to worry about the input leakage. Not only that, we had to route groove on the PCB to limit creepage current.

Trust me, if your Rf is 1M, you don't have a reason to use a J-FET. Confirm this that the Rf is 1M ohm, you can tell your professor that you don't need a J-FET! Get the data sheet of OP-97 and you'll see how low the input bias current is. It is in pico amp range, which is nothing if you try to detect 100nA full scale.

You follow the op-amp theory? You need that for your presentation.

 

[rama1001]

Yes, I know much about op-amp but bit worried about J-fet...now ssome thing i understand and i hope that will enough..

 

[yungman]

Nothing to worry. Seen these many times. All the FET input op-amp are mostly for this purpose. As I said, I spent many years designing detector circuits and had design many trans-impedance amps ranging from 400MHz wide band to 10EE-14A current Faraday Cup amps where the Rf is up to 10G (10EE10) ohm. Verify that your Rf is 1M and you have nothing to worry about. I can find a bi-polar op-amp to do this job for you!

People have a mis-conception that if you want to detect low current, then the input bias current of the amplifier is the most important thing. I can tell you that is not so. It is the input current drift due to temperature that is important. Say if you need to detect 100nA like your case, an op-amp that need 1nA bias current is plenty good as long as the input current drift is small. FET input is actually bad on current drift. They draw pico amps at room temperature, but if you heat it up, it start drawing 1nA ( example only). It will create 1% error even for your case due to temperature. Look at the bi-polar op-amp like OP-97, the input bias current is in 10 to 100 pA range, but the temperature drift is very low. It is a lot more dependable. A stable bias current at the input only create a DC offset and can be nulled out. It is the drift due to temperature that is the killer in these kind of trans-impedance. You can take this to the bank.

This is the data sheet of TLO81, look at the input bias current and see the big difference between 25 deg and full temperature range. It varies from pA to nA. This is typical of J-FET input.

http://focus.ti.com/lit/ds/symlink/tl081a.pdf

 

[rama1001]

In our existing system also having very low input signal and that so far we are using JFET which having high input impedance and more sensible to low inputs. The capacitances 2p and 100p are to chared up for coming input low signal and i did not understood what is going on with capacitance 5p(feed-back). what i understod is that feed back capacitor acts like an integrator which accumulates with input capacitances and to input of JFET. Really what that feed back(r3 and c2) is doing over there and how it wil help to the circuit. I understood about resistors r1 and r4 will help to reduce the offset by just varying the values.

you can see the attached present circuit and help me about feed back and input capacitors.

what ever the input parameters i post in first message that we giving from function generator to check the expected results(40mv-100mv) in real time i.e we connect these circuit directly to the detector in next period infact this information is helpful to analyze yourself.

 

[skeptic2]

Here is a detailed explanation of how a charge amplifier works.
http://sales.hamamatsu.com/assets/applications/SSD/charge_amp_kacc9001e01.pdf

 

[rama1001]

what is the use of JFET in that circuit its only for high input impedance and what the op-amp is doing and i know only that the coming low charge signal from detector will appear at the input of JFET and it has input impedance which will convert that to certain voltage. then what feed back and op-amp is doing. fur further input parameters see the first message and also follow the circuit diagram named as second.doc

 

[yungman]

In our existing system also having very low input signal and that so far we are using JFET which having high input impedance and more sensible to low inputs. The capacitances 2p and 100p are to chared up for coming input low signal and i did not understood what is going on with capacitance 5p(feed-back). what i understod is that feed back capacitor acts like an integrator which accumulates with input capacitances and to input of JFET. Really what that feed back(r3 and c2) is doing over there and how it wil help to the circuit. I understood about resistors r1 and r4 will help to reduce the offset by just varying the values.

you can see the attached present circuit and help me about feed back and input capacitors.

what ever the input parameters i post in first message that we giving from function generator to check the expected results(40mv-100mv) in real time i.e we connect these circuit directly to the detector in next period infact this information is helpful to analyze yourself.

Who design this circuit? So this is supposed to be a charge integrator?...Because it got to be the strangest charge integrator I have ever seen! Who ever design that must never design a real circuit...no offense to the teacher?? Read Skeptic2's link. Hamarmatsu is about the biggest detector company out there. What is shown is the trans-impedance amp and/or charge integrator amp that everyone one else use. The feedback capacitor...C2 in your diagram is ALWAYS used as the integrator capacitor in the standard design depend on the value. When use as trans-impedance amp, the capacitor is smaller and serve as a zero to compansate for the capacitance of the detector at the input for stability and noise reduction purpose.

You really should tell us more on what is the ultimate source that drive this circuit, what kind of detector. We are going in circle on this. I am glad you reposted the schematic because Rf is 10M instead of 1M that I thought I remember.

For a charge integrator, that make a little more sense to have a j-fet input. But you better keep the temperature close to 25 deg C. As I showed you the drift. An integrator integrate current, you cannot affort the have a lot of leakage.

And you supposed to explain how this circuit work as a charge integrator?! If that is your requirement and your grade depend on it, then avoid talking about how the circuit works and concentrate on C2 is to put back the zero to offset the pole caused by the big C3 ( which supposed to serve as the integration cap!). The j-fet at room temperature have very low leakage current so it does not alter the input charging current.

Read the article from Skepic2, that is how the amplifier should be. The only thing I added is the input 50 ohm resistor in my drawing. In real life, because we detect very low current and 50 ohm is not going to affect the bias of the detector and it really serve as separation of the input capacitance from the input of the amplifier. That is the main cause of instability. For Rf = 10M, TLO81 still work, just keep it close to room temperature.

 

[yungman]

what is the use of JFET in that circuit its only for high input impedance and what the op-amp is doing and i know only that the coming low charge signal from detector will appear at the input of JFET and it has input impedance which will convert that to certain voltage. then what feed back and op-amp is doing. fur further input parameters see the first message and also follow the circuit diagram named as second.doc

The J-FET has very low gain. The op-amp serve as the main gain for the circuit. It is run at open loop so the gain is very high...in order to give you the accuracy of the feedback circuit. Remember the accuracy depends on the open loop gain?

AD815 is a 50MHz amplifier. That is playing with fire! The integrating cap is supposed to be C3, the speed of integration must be quite slow to want to use such a fast device.

 

[rama1001]

This is big project to mesure the Ra detection. the first stage of this power supply and the output of that is -200v which will given to the detector placed in a dome shaped interior(because we are using -200 due to attract the positive charged particles which are decomposed by Ra). then next is our design CSA which will convert coming low charge to mesurable voltage pulse(40mv to 110 mv). Dont tell me like reading hamamatsu material. i know that very long but we are trying to generate new system. continuing next is shaping part to get well shaped pulse and next is peak detector to catch the peaks with reset. next the digital part will start to enhance the results by histograms and i can explain each part because its so big. Any way we know need to discus about digital part just the whole system is designed its working.

Now tell me clearly every time if i ask about JFET you are saying about temperature maintaince and leakage current. I did not understand about what u r talking in the perspective of leakage.

Next time can not explaine more about other parts because i have a presenation by tommarow. so i feel this may be the last meassgae i am going to ask you, please tell me what you guess on why JFET is used(dont tell me about temperature and high input impedance) and what abot feed back and op-amp.

May be you think, how this guy done this system without knowing about circuit working. This because of force by instructor and just i soldered as like what they have given materials. may be i will attach the correspoding PDF if size is ok.

may be we can discuss after two days about whole system in clear manner but right now i can't so please tell me about that questions what i have posted in clear way also not write about dominant poles and zero concepts. just i need only working function.

 

[yungman]

This is big project to mesure the Ra detection. the first stage of this power supply and the output of that is -200v which will given to the detector placed in a dome shaped interior(because we are using -200 due to attract the positive charged particles which are decomposed by Ra). then next is our design CSA which will convert coming low charge to mesurable voltage pulse(40mv to 110 mv). Dont tell me like reading hamamatsu material. i know that very long but we are trying to generate new system. continuing next is shaping part to get well shaped pulse and next is peak detector to catch the peaks with reset. next the digital part will start to enhance the results by histograms and i can explain each part because its so big. Any way we know need to discus about digital part just the whole system is designed its working.

Now tell me clearly every time if i ask about JFET you are saying about temperature maintaince and leakage current. I did not understand about what u r talking in the perspective of leakage.
The main reason of using the FET is because of the low input bias current. Nothing else.
Next time can not explaine more about other parts because i have a presenation by tommarow. so i feel this may be the last meassgae i am going to ask you, please tell me what you guess on why JFET is used(dont tell me about temperature and high input impedance) and what abot feed back and op-amp.
Low input bias current!
May be you think, how this guy done this system without knowing about circuit working. This because of force by instructor and just i soldered as like what they have given materials. may be i will attach the correspoding PDF if size is ok.

may be we can discuss after two days about whole system in clear manner but right now i can't so please tell me about that questions what i have posted in clear way also not write about dominant poles and zero concepts. just i need only working function.

I thought I said very clearly that people use FET as input for low bias current. All the rest is just my experience of the short coming of FETs only.

The stuff below has nothing to do with your question. Read it when you have time after tomorrow. I see you are very despirate today!

I have to take a closer look at the PDF file, I opened it and look at it for a minute. If you look at figure 8, it is totally different from the schematic. The C3 in your schematic is actually the gate source capacitance, not an external cap. This is one of the cap that always there that can cause instability when Rf is too large. Cf is partly used for compansating this with a zero. But in your ciruit, the designer actually put a 100pF REAL cap there! That is a day and night difference. I don't even agree with the assertion of the I_{gen} for rejecting power supper noise. But don't take those people too seriously. They are not always correct.

I did published a paper of my design in American Institude of Physics on the Ultra fast resistor anode decoder of the work I did in 1996 which the main part was a resettable charge integrator:

http://rsi.aip.org/rsinak/v71/i11/p4144_s1?isAuthorized=no

Don't take those as the golden words! More like minipulation of words ! My name is Alan Liu on it.

In the paper, OP-27 is a much suitable amplifier. Hope that clear up your question.

 

[rama1001]

its ok now with that discription. But as i said, first we checked our CSA with function generator by the input parameters what i have given in first scrap. But just i am thinking in my mind about Ra which decomposes and releases one alpha and may be one more beta particle from detector(dome shaped) will have same charge as what we testing the circuit with 111mv with function generator or any difference. if those two are same then what is the purpose of CSA, because it also output almost same (originally needed range 40mv-80mv).

what i know is generally we use CSA for converting the coming charge pulses to voltage pulses which will enhanced by other parts. is it right or not.

one more doubt about how the released charge partcles(in our case two particles) will get skecthed up like two peaks(means how they transferred at input of CSA in that fashion) which starts with low height peak(alpha) next bigger peak(beta).

is there any difference between charged particle pulse and voltage pulse . I guess one thing that the relese particle have some energy may be that energy will count as pulse. if so how we can describe that in good way(i am like idle for those ocations)

 

[yungman]

its ok now with that discription. But as i said, first we checked our CSA with function generator by the input parameters what i have given in first scrap. But just i am thinking in my mind about Ra which decomposes and releases one alpha and may be one more beta particle from detector(dome shaped) will have same charge as what we testing the circuit with 111mv with function generator or any difference. if those two are same then what is the purpose of CSA, because it also output almost same (originally needed range 40mv-80mv).
The only thing I can think of is the 2pF C1 that is so small the every time the signal generator pulse, it only put in a little packet of charge (Q=C_1 V_{gen}. As I said, I disagree this way of testing.
what i know is generally we use CSA for converting the coming charge pulses to voltage pulses which will enhanced by other parts. is it right or not.
Yes.

one more doubt about how the released charge partcles(in our case two particles) will get skecthed up like two peaks(means how they transferred at input of CSA in that fashion) which starts with low height peak(alpha) next bigger peak(beta).
Not familiar with the dual pulse in your case. Pulse pair resolution is a big topics in the pulse counting spectroscopy. This is a totally different subject you don't want to get in for now. I actually published another paper of how to lower the dead time between two close pulses in the CAMECA SIMS.
is there any difference between charged particle pulse and voltage pulse
Charge particles are just as the name...charges. It is a packet of charges. When a charge pulse drive into a resistor, it become a voltage pulse! A simple resistor is the basic form of trans-impedance amp.

. I guess one thing that the relese particle have some energy may be that energy will count as pulse. if so how we can describe that in good way(i am like idle for those ocations)

All ions release in form of charge pulses. So most of the pulse amplifiers are used to amplify the pulse and convert them into voltage pulses for counting. Sounds like what you have is very high magnitude pulses. We usually use either electron multiplier to amplify the pulse before going into the amplifier. Sometimes we use Channel Plates follow by a Resistor Anode Enclode to do amplifying and position decoding before driving into the amplifiers. I am not familiar with your project so let's just stop here before I confuse you more.

Following is not for tomorrow either:
Are you using this for pulse counting? If so, at least I can understand why they use AD817 for high speed. Actually charge pulse is quite high speed with sub nano seconds rise time. We never use integrator. Integrator is to integrate a collection of pulses. For pulse counting, you amplify each and every individual pulses. We use 400MHz or faster amplifiers to do pulse counting. In the early 90s before all the monolithic IC amplifiers came out, I had to design trans-impedance amp with descrete GaAs FETs. That is a totally different animal.

Alan

 

[rama1001]

no what u r talking about pulse amplifier is not relevant to this project,,..but we are unsing pulse counting in our project by making the peak detector with reset and also may be in digital part(AVR32 and labview) to show the output as a graph with count vs energy.

thank you ..you gave me such a good information..and again u created me some doubts.. i will post that after presentation

 

[yungman]

Good luck on your presentation today.

 

[rama1001]

Hi,
Back again here and finished my presentations with full system is working. i need ask you some thing about analogue circuits.

I studied so many materials and some of those are describing about analogue corcuits for many purposes. In part of that everytime they explaine about pole ZERO concepts(whenever i seen those words in paragraph i feel that is **** ). I need to overcome that by your help.

First of all if you are designing any system which mixed up with analogue circuits. how can i decide myself and analyze after seeing that circuits(like that resistor will cause for dominant pole or may be it can make zero) like you are analyzing now.

Dont say me like you need to draw bode plot for that system. tell if there is any shortcuts. and how you are analyzing circuits by telling those points. how can i improve in that area..