Help Building 4-Bit Searching Circuit

[pags920]

Hello, I am brand new to this forum. It looks like there are a lot of people that might be able to help me on this project.

I need to build a 4-bit searching circuit. The circuit takes a 4-bit word and searches a 4x15 memory for that word. It will have two modes, a Load Mode, where the words are loaded to the memory, and a Search Mode that searches the memory for a given word coming from data switches (using a digital trainer). When the circuit finds the first matching word in the memory, the search process should be stopped and the memory location is displayed on a 7-segment display and an LED is triggered on, indicating that a match was found. Otherwise, if a match is not found, the search should be stopped after testing all words in memory and the LED is triggered off, indicating a match wasn't found.

Our TA has hinted that we can use a Comparator Circuit, that we previously did in our lab.

As of right now, I can create the circuit for Load Mode, as all it is was a previous lab that we did. But the Searching Mode is what I am stumped on. I am not sure if there is a way for the circuit to search automatically or manually using logic switches.

I guess the question that I am asking is how can I create a circuit that does both Load and Search? Do I need to use flip-flops or am I overthinking the whole thing?

My current circuit consists of:

1 - 2114 1K x 4-bit static RAM IC
1 - 74LS193 synchronous up/down binary counter IC
1 - 9368 decoder-driver IC
1 - 7-segment display

Any help or hints would be most helpful.

 

[vk6kro]

Welcome.

One way would be to use EXCLUSIVE-OR gates. One is the Cmos 4070.

These have 4 gates per chip and each gate has 2 inputs.
If the two inputs are the same, the output is zero. If they are different, the output is 1.

So, you could clock the input of your memory chip with a binary counter (a 4040 Cmos chip driven by a NAND gate oscillator) connected to the address lines, and take each of the 4 bits to a different XOR gate input.
The other input of each gate would go to a dip switch with your voltage comparison on it.

Then you have to combine the outputs.
If you had diodes from the outputs to a common load resistor, if any of the outputs was still high, the output would be high and you could use this to keep searching.
If it was a zero, you could stop the clock and indicate that all the outputs are the same as your logic switch.

 

[pags920]

Welcome.

One way would be to use EXCLUSIVE-OR gates. One is the Cmos 4070.

These have 4 gates per chip and each gate has 2 inputs.
If the two inputs are the same, the output is zero. If they are different, the output is 1.

So, you could clock the input of your memory chip with a binary counter (a 4040 Cmos chip driven by a NAND gate oscillator) connected to the address lines, and take each of the 4 bits to a different XOR gate input.
The other input of each gate would go to a dip switch with your voltage comparison on it.

Then you have to combine the outputs.
If you had diodes from the outputs to a common load resistor, if any of the outputs was still high, the output would be high and you could use this to keep searching.
If it was a zero, you could stop the clock and indicate that all the outputs are the same as your logic switch.

I have access to a 74LS86 Quad Two-Input XOR IC. Would that work the same way?

And I am not too familiar with when you said "clock the input of the memory chip with a binary counter." But after looking at one of our previous labs, I think I understand what you mean by clocking the memory with a counter.

By NAND gate oscillator, in regards to NAND gates, I have access to a 74LS00 Quad-Two Input NAND IC. How would you implement that? Sorry for asking, but I haven't been taught anything about a "gate oscillator."

 

[vk6kro]

You would have something like this:

[PLAIN]http://dl.dropbox.com/u/4222062/clocking%20memory%20chip.PNG

A pair of 74C00 NAND gates drive a 4040 binary divider and some of the output of this drives the address lines of a memory chip.
Each address accesses a memory location and the contents of the memory location are available at the data output pins.

This is where you would connect the Exclucive-OR circuitry we were discussing earlier.

The 4040 is a CMOS chip, so you would probably need to use CMOS for the other chips as well.

 

[pags920]

Ok, how would I go about in starting this design?

 

[vk6kro]

I have added the exclusive OR circuitry to the above diagram.

If you read through the earlier posts, it may make more sense.

The NAND gate clock speed depends on the values of R and C. 470 K and 0.1 uF would be typical values.

You could use a 74LS193 instead of the 4040 since you are already using one of these.

 

[pags920]

I have added the exclusive OR circuitry to the above diagram.

If you read through the earlier posts, it may make more sense.

The NAND gate clock speed depends on the values of R and C. 470 K and 0.1 uF would be typical values.

You could use a 74LS193 instead of the 4040 since you are already using one of these.

I am using a Digital Trainer, so it has a CLK output built in. I would take that output and connect it to the input of the LS193, correct? Would I connect that to the Count Up/Down Input?

 

[vk6kro]

There is a 3rd NAND gate which controls the flow of pulses from the clock. (see diagram).

This is so that when the XOR gates decide there is a match, the clock pulses are stopped and the value of the memory location can be read out on a digital display.

BUT this is your assignment and you will need to take it from here.