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High Impedance in Verilog?

  1. Sep 27, 2007 #1
    High Impedance in Verilog????

    1. The problem statement, all variables and given/known data

    Provide the correct Verilog text for encoding the following numerical values:

    A) A 16 bit hexadecimal with all positions in the high impedance state:

    B) An unsized hex number BEEF

    2. Relevant equations

    Verilog Problem. There is no relavant equation to be used.

    3. The attempt at a solution

    What the.. I didn't even know a variable can literally be declared as high impedance. I thought high impedance state occurs when the variable is neither off or on.

    Also, I thought the variables you declare in verilog MUST be sized.

    How are these accomplished?
    Last edited: Sep 27, 2007
  2. jcsd
  3. Sep 29, 2007 #2
    You actually can have the states as high-impedance. In your case, it would be


    would work.

    There is no such thing as unsized hex number. Even if you forget to declare the size, by default, verilog would size it as 32 bit.
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