How Are Transistors Positioned on Computer Chips?

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Discussion Overview

The discussion centers on the methods and processes involved in positioning transistors on computer chips, including the creation of masks used in chip manufacturing. Participants explore the intricacies of chip architecture, the precision required for placing billions of transistors, and the historical context of mask creation.

Discussion Character

  • Exploratory
  • Technical explanation
  • Historical

Main Points Raised

  • One participant expresses curiosity about how transistors are precisely positioned on chips and requests elementary explanations.
  • Another participant provides a link to a resource that may help clarify the topic.
  • A participant notes that the architecture image is encoded into a mask, leading to a further inquiry about the mask's creation process.
  • It is mentioned that masks are drawn using computer-aided tools at a larger scale and then reduced optically, with each mask corresponding to a single layer of the circuit.
  • A participant shares a personal anecdote about hand-drawing masks in the 1980s, detailing the labor-intensive process involved.
  • There is a mention of a shift from junction diffusion to ion implantation in modern chip manufacturing for improved doping precision.
  • Another participant humorously expresses a desire for advanced machinery to enhance their setup.

Areas of Agreement / Disagreement

Participants share various insights and experiences related to chip manufacturing, but there is no explicit consensus on the best methods or processes discussed. Multiple perspectives on historical practices and modern techniques remain present.

Contextual Notes

Some discussions touch on the evolution of techniques in chip manufacturing, such as the transition from junction diffusion to ion implantation, but the implications of these changes are not fully explored.

Demystifier
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I sort of understand how a computer chip works and what is its architecture. But how is it made? I mean, a chip contains billions of transistors, each having a microscopic size. Each transistor must be put at a very precise place. How do they control the position of a single tiny transistor? And how do they do it for such a big number of them?

A link with an elementary explanation of this would also be welcome.
 
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It's drawn using computer-aided drawing tools at a much larger scale then reduced optically.
Edit: The circuit is built up in layers, and each mask describes a single layer.
 
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After all that work the first good ones are framed.:-p
IMG_20160927_073346604.jpg


and the bad ones are made into keychains.:frown:
http://www.chipsetc.com/intel-keychains-page-3.html
 
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nsaspook said:
After all that work the first good ones are framed
98% yield -- nice! :smile:
 
One of my first jobs in the 1980's was drawing the mask for a chip by hand. Each mask used 4 sheets of A0 drawing paper joined together and was drawn with a coloured pencil. The drawing was then digitised and fed to a machine that looked like a very large flat bed plotter. Instead of a pen it carried a knife blade that cut through the top layer of a two ply sheet of plastic film. The top layer was red and the bottom clear. A room small full of people were employed to peel off the top layer of red film leaving transparent tracks. The resulting sheet was then photographically reduced to produce the mask used in production. Very time consuming.
 
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A little old video, but from someone who knows; Fairchild.

 
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dlgoff said:
A little old video, but from someone who knows; Fairchild.



That's a great old video but junction diffusion has been replaced in many steps by ion implantation because of the level of doping precision needed in modern devices.
 
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  • #11
nsaspook said:
... junction diffusion has been replaced in many steps by ion implantation ...
I want one of those $5x106 machines to replace my little set-up. :oldbiggrin:
 
  • #12
dlgoff said:
I want one of those $5x106 machines to replace my little set-up. :oldbiggrin:

We still have one (vacuum evaporator) that's used for sputter coating non-conductive specimens for electron microscope inspection.
 
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