How Do You Design a JK Flip-Flop Synchronous Up/Down Counter?

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The discussion focuses on designing a synchronous up/down counter using J-K flip-flops to count through specific sequences based on an input switch. The user is struggling to adapt an existing circuit meant for a simple counting sequence to the required complex sequences. Suggestions include using three bits and leveraging the toggling properties of J-K flip-flops, but the user finds their current approach messy and overly complicated. A recommendation is made to create a next state Karnaugh map table to simplify the design process and eliminate guesswork. This method could provide a clearer path to achieving the desired counter functionality.
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Exam question:

Use J-K flip-flops to design the logic for a synchronous up/down counter that counts "up" through the sequence 1 2 6 3 5 7 f the input switch UP is 1, and "down" through the sequence 7 2 1 5 3 6 if UP is 0. Verify that the counter is self-starting.


What I know so far:

Ok so in my book I've found a similar circuit, except it's to count through the sequence 1 2 3 4 and so on. And I'm not sure at all how I'd go about changing the circuit to work for the question above. The circuit I have is:

article1.sync_bin_c.gif


Any ideas?
 
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Hi Mark200, welcome to PF!

Hmmm...so it looks like you'll need three bits. And you want to go through the sequence:

001
010
110
011
101
111

It looks like the circuit you have makes great use of the fact that setting J = K = 1 toggles Q to change state, and setting J = Q = 0 keeps it the same. So I would expect that what would change would be which output of which AND gate goes where. That's all I've got though, short of actually trying to draw out different circuits.
 
Ok I'm afraid I'm going to need to ask for more help on this question! I failed my exam and I have to do a repeat exam, and it's tomorrow hah. And this question came up on the original exam!

I've been trying to figure out how to do it. I found a way, but it involves having about three logic gates for every single input and it's extremely messy. There must be an easier way. I tried to scan my work so far in but my scanner isn't working! I've thought about changing where the outputs go but I don't think that'll work.

Any ideas?? As much help as possible would be great! Even if it doesn't come up on the exam tomorrow it'd just be a relief to finally know how to do this question
 
Mark200 said:
Exam question:

Use J-K flip-flops to design the logic for a synchronous up/down counter that counts "up" through the sequence 1 2 6 3 5 7 f the input switch UP is 1, and "down" through the sequence 7 2 1 5 3 6 if UP is 0. Verify that the counter is self-starting.


What I know so far:

Ok so in my book I've found a similar circuit, except it's to count through the sequence 1 2 3 4 and so on. And I'm not sure at all how I'd go about changing the circuit to work for the question above. The circuit I have is:

article1.sync_bin_c.gif


Any ideas?

Mark200 said:
Ok I'm afraid I'm going to need to ask for more help on this question! I failed my exam and I have to do a repeat exam, and it's tomorrow hah. And this question came up on the original exam!

I've been trying to figure out how to do it. I found a way, but it involves having about three logic gates for every single input and it's extremely messy. There must be an easier way. I tried to scan my work so far in but my scanner isn't working! I've thought about changing where the outputs go but I don't think that'll work.

Any ideas?? As much help as possible would be great! Even if it doesn't come up on the exam tomorrow it'd just be a relief to finally know how to do this question

I'm sure it's a bit late for your exam. But instead of trying to find some ad-hoc jerry-rig that works, why don't you make a next state karnaugh map table with variables s, y0,y1,y2 from which you can solve for the J and K inputs? Takes a little time but also removes all the trial and error guesswork.
 

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