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Event driven Verilog simulations

  1. Aug 12, 2010 #1
    I know Veriog simulators are event-driven and what matters is the moment that event happens.

    Suppose we have a code like,

    module inv (in, out);
    input in;
    output out;

    wire inv_s1;
    reg out;
    assign inv_s1 = ~in;
    assign out = ~inv_s1;

    endmodule

    My question is does inv_s1 maintains any state between the events ?
    Let's say in=0 initially, and it gets changed to in=1. It propagates through inv_s1 and changes the state of 'out'. 'out' is declared as reg so that it maintains some state all the time, but what happens to inv_s1 which is declared as wire once the event settles ?
    Does it still maintain the value 0, or it has no value or state assigned till the next event happens ?

    More specifically, what value am I supposed to see on inv_s1 if I poke inv_s1 at #25 in the following simulation ?

    initial begin
    #10 in = 0;
    #10 in = 1;
    #10 in = 0;
    #10 $finish;
    end
     
  2. jcsd
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