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How to think about ground planes

  1. Dec 16, 2011 #1
    I recently had a discussion with a guy who believes that by putting a big slot in his PCB ground plane he will protect his analog domain from the noise originating in his digital domain. I don't agree with this view (hence the discussion), for various reasons, but to keep this post on point I want to focus on the guy's analogy---or way of thinking about the ground plane.

    His reasoning went something like this: When a digital IC switches from one state to another, the device will produce a large di/dt that depletes the immediate area (and decoupling cap) around the IC for charges. This, in turn, disturbs neighboring charges ("pulling" them in / "pushing" them out, gah) and creates waves from the point in the ground plane and outward just like a stone dropped in a pond. Even with a decoupling cap, the current needed at the instance the IC changes states will be almost infinite so it will cause these "waves" in the ground plane during the first few nano-moments, etc..

    I'm not even sure if that's an analogy or what it is. I tend to think in terms of currents and where/how they return to their source, so this picture of a "pond of charges" or what the hell it is, bothers me.

    I tried to play the game of analogies and suggested it was more like removing a drop from the Atlantic, and that the pond analogy was more accurate if you added Hurricane Katrina to the picture. The discussion didn't go anywhere from there... (I'm just an engineer, not a particle physicist)

    So, any thoughts on IC injecting and removing charges from the ground plane and creating ripples across the plane?
     
    Last edited: Dec 16, 2011
  2. jcsd
  3. Dec 16, 2011 #2
    Usually an analog ground is seperated from a ground plane with a small trace. He has the right idea generally, because you have to be careful for ground loops where the current in ground will travel the shortest distance and create voltage drops along the ground (the copper has parasitic inductance and capacitance, so ground is more like an antenna/transmission line than a lumped circuit at high frequencies). But on the other hand I have been told as a general rule of thumb to make ground planes as big and filled as possible, which I try to do unless there is an application note asking to do a special ground isolation like in the case of a ethernet magnetics.

    I thought of it this way, if the ground plane is acting like an antenna, cuts in the ground will reduce the wavelengths that can travel along the conductor. I don't know if that puts any thoughts in your head about it.
     
  4. Dec 16, 2011 #3
    What kind of logic is he using, CMOS?
    What is his clock frequency?
    How wide is his Vcc trace?
    Does he use decoupling capacitors?

    The effect that you describe I don't think is caused by a large di/dt but by a large switching current. The datasheet should tell you what the switching current is and what the switching time is. That should give you an idea of the magnitude of the problem. (You can learn a lot from a datasheet.)

    "Almost infinite" is interesting concept and brings to mind a Woody Allen quote, "Eternity is a long time, especially towards the end."
     
  5. Dec 16, 2011 #4
    Could you expand on the ways you think the charge-makes-ripples-in-the-ground-plane way of thinking works, and how it is useful. Think a lonely driver and a load fairly close together on a large PCB---the "pond"-model predicts that the pair of them would create noise for sensitive analog devices on the other side of the board. By what mechanism would a switching IC "pollute" the entire ground plane?
     
  6. Dec 16, 2011 #5
    Anything that switches current at a fairly high frequency. Yes, you can assume decoupling. But what I'm trying to establish is whether or not noise spreads in the ground plane as the rings from a stone in a pond.

    I'm unable to see beyond the fact that the driver and its decoupling capacitor (which is the source here) and a load will form closed loops where the current will flow. Only if you stupidly put you sensitive analog device so that its return current passed through said loops, will the digital devices cause noise problems for the analog device. That's my take on it, anyway.
     
  7. Dec 16, 2011 #6
    Isn't a large switching current also a larger di/dt?
     
  8. Dec 16, 2011 #7
    I've never measured it but as any good designer will tell you, you try to keep digital and analog circuits separate so I guess the answer is yes. However the noise on Vcc should be greater by the relative resistivity of the Vcc trace versus the ground plane. So normally I would expect the switching noise on Vcc to be orders of magnitude greater than the noise on the ground plane. Likewise the greater the di/dt of the switching current, the more effective decoupling caps should be.

    The usual way of dealing with that problem is to join the analog and digital ground planes a single point.
     
  9. Dec 16, 2011 #8
    I designed a lot of mixed signal circuits that contain sensitive analog and high speed digital and I did signal integrity contracts before in helping pcb layout. I personally never cut grounds. I always use single ground plane and I never have problem.

    BUT this is an interesting question. Remember if you look at any logics family other than ECL, they always have push pull output. During switching there is always a very short time that both the top and bottom transistor turn on at the same time and large current drawn for that split second ( say nS or even pS). This is particular bad in CMOS logics where the turn-on threshold is unpredictable. You can find this in data sheet on Vcc current vs switching frequency. You'll see at some frequency, CMOS logic over take TTL at high switching frequency even though at static, CMOS do not draw nearly as much as TTL.

    Noise generated everytime you switch output state regardless whether you sent the signal out to another part of the board or not. The di/dt is just as great regardless you switch in high frequency or one switch. This signal travel from the positive Vcc pin back to the Ground pin of the same IC. Theoretically if you have perfect bypass path, the noise will just travel from the Vcc to GND pin of the IC and going nowhere else. But we are talking about frequency components that reach into microwave frequencies and bypass cap really don't work so well. So noise do come out.

    Back to your friend's assertion. Let's consider you do have a power and ground plane that connect to the IC's Vcc and GND pins resp. The noise will not come out like a stone drop in the pond and spread out to all direction. This is all governed by EM theory and transmission line theory. Whenever a signal come out that, there is always a source and a return, there is NO EXCEPTION on this. In this case, the source of the Vcc of the IC is the input power of the board, the return is the return of the power supply that power the board. Basically any noise that is not bypassed by the bypass cap is going to travel back to the power source input of the pcb. The question is what path the noise takes to the power source. EM theory govern that it will take the shortest distance from the IC to the power source AND the path is governed by the loop that encircle the minimum area. This mean that the forward and the return signal are right on top of each other. It behave exactly like stripline even though it really is a power and ground plane. Bottom line, the noise signal and return will find the shortest path from the IC to the power input of the pcb AND the source and return signal are travelling on top of each other like a stripline. Here are the reasons:

    1) The reason of finding the shortest path is very simple. Copper do have resistance. Current density is highest at the path of lowest resistance and so it would be the shortest and most direct path!!! It is not going to go all directions and then go to the power input point to the pcb.

    2) The reason why the signal and the return path always follow closely with each other unless there is an interruption is because the voltage/current signals travel as EM wave, not really as current or voltage like people want to think ( this is more complicated and not needed here). The current and voltage is only the consequence of the boundary condition of the EM wave travelling down the path as surface current density given by the EM boundary condition. EM wave do travel in a single path, so the induced current on both the power plane and ground do follow the path of the EM wave and keep closed to each other whenever possible. That is if there is no interruption.

    In simpler term: In signal integrity engineer term, the signal path choose the path of LEAST INDUCTANCE. Which means the path that enclose the minimal area...........Which imply they travel close the each other...........one on top of each other.


    That said. To me, the best way is to design the pcb stack up that the power and ground planes are on top of each other and separate by 5mils of FR4 only. This will produce larger distributed capacitance between the two planes and this having large surface area, will produce almost an ideal cap ( at least in GHz range) that able to give a good bypass path between the Vcc and GND pin of the IC. Noise from Vcc to GND pin will almost go straight between the pins and not out. If you don't have a good coupling or power is not on a plane but only a trace, then you better worry more as signal not only on the ground but also the power trace.

    Now come to the point of separate analog and digital ground. To me, this is more dangerous than you think. Read the 2) point that I gave again, if you make a cut in the wrong place that cause a disruption of the EM wave, the forward and return path of any signal trace will be forced to run a separate paths and increase the area enclosed and so forming a loop. AND you know how good a loop antenna in radiating EM wave!!! The EM theory described in 2) apply to signal output that drive to other parts of the board. The forward and return path always stay close unless that is a break and that's where the problem starts.

    Think of if you have cut grounds, and the digital run on top from one ground plane to the other, return signal is disrupted and has to find a different path to complete the loop. You'll have interference all over. Hope this give you a better idea.

    So in summary, signal DO NOT propagate out like stone drop in a pond. Separate ground plane is only good if you know exactly how the signal travel...........Believe me, people think they know a lot more than they really do!!!! But short of that, use single ground plane, make the power and ground plane close to each other to form an ideal cap to take care of the bypass when the 0.01uF cap starting to fade out.

    With good layout technique, interference is not a problem. If you look at the current distribution on the ground plane under a microstrip ( exactly the same as signal trace running on the surface of a pcb with ground plane under), 90% of the current is contained within 4 trace width on each side of the trace with normal stackup. Meaning if your sensitive trace is greater than 6 to 7 trace width apart, you are pretty safe. There are so many mis-conception about grounding it's not even funny. Then the matter got worst when those professors that don't have a day in real life design is teaching electronics. Look at all the books, they concentrate on all the fancy theories and they treat power and ground as just a connection!!! Power and ground are the most difficult part of the design. If you take care of this, circuits actually work as describe in the books!!!! All the problems mostly stamped from implementation of the circuit in real life............power and ground is not just a point..........they are actually part of the circuit and that usually the part people get screwed.......pardon my words.
     
    Last edited: Dec 16, 2011
  10. Dec 17, 2011 #9
    I want to add, I design a 24" flex circuit ( flexible pcb) of about half inch wide. Inside, I have two 50Ω RF lines, a pair of 90Ω USB and two pairs of 110Ω Firewire( each FW is two pairs of differential lines). I designed the layout and stackup and I get over -25dB cross talk isolation between all different signals testing at 1.8GHz, that is very good. I designed so the dielectric thickness of the strip line is as thin as possible to accommodate a 4mil trace for the Firewire lines. That was the gating factor as 110Ω differential impedance require very thin trace and I don't want to use 3mil as the conductance loss start to build up and the eye start to close at the receiving end.

    If I were to change the spec of the Firewire to 100Ω, I should be able to get even better result. There goes to show how close you can put digital signal and analog trace together. This is 24" running side by side!!!! I won't be insisting on cutting ground because you stand to screw up much more than it will help.
     
  11. Dec 17, 2011 #10
    I was really thinking about this over night as EM fascinate me. Please join in for discussion as this is really my opinion and I am not sure this is correct.

    Let's say you are using a 4 layer board and traces are on the top and bottom layer only. power and ground as internal plane close to each other like what I said about only 5mils apart. My assertion is the trace on the top and bottom will not see any spike from the di/dt as mentioned in this post. This is my reasoning:

    As I said before, it is the EM wave that propagates, EM wave in this case only confined in between the power and ground plane that form a GUIDED structure( think parallel plate transmission line). There is NO SURFACE CURRENT DENSITY on the top side ( or bottom side) of either plane. This is because you cannot have a guided structure on the top or bottom of the pcb to sustain the EM wave caused by the di/dt.

    You might argue that current can conduct from bottom of the copper plane to the top, but that would not happen. The reason is at this frequency, current is absolutely confined as surface current. There is no penetration into the copper. If you want any surface on the top side and bottom side of the planes of the pcb, you are going to have to have EM wave propagation. This will not happen as there is no structure to promote an EM wave of the di/dt on the top and bottom side.

    That said, my conclusion is the trace on the top and bottom layer should not see the di/dt effect. I am going to see whether I have PM some high power physics people like Cabraham and StevenB in the Classical Physics to comment on all my assertion, hope they are still hanging around here and can join in.
     
    Last edited: Dec 17, 2011
  12. Dec 18, 2011 #11
    Hey Yungman, thanks for sharing your experience. I agree with most of what you say, and find nothing in this thread to support the "pond-theory".

    But, playing the devils advocate for a second I'd like to argue that in a high frequency and/or low decoupling capacitance (be it a discrete device or parasitic trace capacitance) scenario, the switching noise current loop formed by the totem-pole pair and back through the surrounding capacitance will expand in area. I'm picturing the di/dt spikes finding an increasing number of small parasitic caps around the driver, which would mean that a larger copper area (with a finite inductance) would see the di/dt and cause a noise voltage. If you measured the ground voltage at various points referenced to some other stiffer ground, it could appear as if the noise spread as the "pond-theory" predicts. Does this make sense?

    (All of this could of course be remedied by proper decoupling and stackup, so it's still not an argument against a solid gnd plane.)
     
  13. Dec 18, 2011 #12
    Section 7.10, page 173 to 174 of the IEEE publication

    Printed Circuit Design Techniques for EMC compliance, by Mark Montrose

    is entitled

    Ground Slots in Backplanes.

    It discusses this matter and explains why return RF currents have to travel 'the long way round' slots and offers formulae.

    See also page 36 of this publication.
     
  14. Dec 18, 2011 #13
    Can you expand more as I don't belong to IEEE. What is the "long way around".
     
    Last edited: Dec 18, 2011
  15. Dec 18, 2011 #14

    You are talking about a different scenario already. If you have very good bypass around and you have bad bypass on one particular IC, then yes, it will seek the path of least resistance and in that case, will be from the surrounding bypass cap. I am talking about the ideal case where you have one IC with tolem poll and one source point. It's about the path of least resistance.

    Even in my original reply, if you are looking at the moment the noise come out, it is spreading in all direction, but quickly turn toward the direction of least resistance. Think about the electric field of a simple dipole, at the moment the field leaving the +ve charge, the field lines are radiate in ALL directions evenly, but when they travel out, it start bending towards the -ve charge.

    Also you have to consider the attenuation of the noise pulse. Theoretically, you never get zero, just how low it is when get the the sensitive analog trace. Of cause given in the perfect world, you will bet better isolation with separate grounds, but you really have to know what you are doing and account with every single signal trace to ensure you get the image current right. One mistake will cause you more problem than the little interference from the residue noise of a single ground plane.
     
  16. Dec 18, 2011 #15
    You don't need to be a member to obtain the book, which has lots of good recent advice/information for pcb designers.
     
  17. Dec 18, 2011 #16
    I have the EMC and printed Circuit Board by Mark Montrose, not the one you mentioned, I prefer using the Howard Johnson and Martin Graham. I know you never like to give your opinion, but can you summerize what the book said so to save us time to read through the whole chapter? If you know what it's about, please tell us.

    I don't know about slotted lines and the materials that I study all prefer single ground planes as I explained. We had a class with a very well known EMC person called Chris Kendell and he talked a lot about grounding. . He was a very sorted after person by companies to work on EMC in the industries as I worked for two different companies that used him as consultant. I interpretate all the ideas with EM theory.
     
    Last edited: Dec 19, 2011
  18. Dec 25, 2011 #17
    I've spent the better part of my life working in precision analog.

    The scope tells all. If you allow fast rise-time signals to route over your analog ground plane or to carry logic currents through your analog ground plane, you will have fuzzy signals, noisy A/D channels, and sometimes DC offset in your paths. Then, you'll wonder why your waveforms never look as pretty as those supplied in the data sheets.
     
  19. Dec 25, 2011 #18
    If you talk about you have separate ground plane and you have digital signal run over the analog ground plane, yes then you have big problem as I explained before. This is the reason I recommended not to separate ground unless you know exactly what you are doing. It is easy to talk in the book about how to route the trace and keep away from the analog ground. In real life, it is not as easy, you make one mistake and there you go.

    As I said before, if you have one solid ground plane and make sure you don't have separate power plane right under the traces, you are safer. Image current follow the signal trace and don't spread out.
     
  20. Dec 25, 2011 #19
    Well, that would depend to how the current (that is being injected) is supplied. In general, yes, you can have ripples in the ground and power planes, yes they travel like waves in the pond, and yes, they can get into the analog side, and yes you are better off separating the analog power and analog ground from digital power and digital ground with a thin perhaps coiling trace (that would have inductance) or best yet a small inductor, and attaching a capacitor on the analog side. At high frequency you really do have ripples propagating. The power being your vcc.

    edit: albeit the ripple is matched to a ripple in the vcc. When the IC suddenly starts consuming more power, the ripple of lower + voltage at + line and higher - voltage at - line starts off at the IC, goes towards source, reflects there as a ripple of higher voltage (or the voltage equal to vcc), and gets back to the IC. It also reflects off all the capacitors. If you have the capacitor in parallel to the IC between IC and rest of the circuit, it'll pretty much prevent the ripple from going anywhere past that capacitor (or at least decrease the ripple quite a lot). The computer boards are packed full of tiny capacitors for this (well, and some other) reasons. And indeed the image current ripple in ground won't spread out much from the line that is powering the IC.

    Some devices, such as nitrogen lasers, even depend directly on the ripple propagation to set up the moving discharge in the channel.
     
    Last edited: Dec 25, 2011
  21. Dec 26, 2011 #20
    Can you explain in theory about the ground plane ripple like stone drop in a pond that spread to all sides?

    We assume there is bypass cap as in #5, we are talking about higher frequencies that the small 0.01uF bypass cap cannot even cover.
     
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