Inductive load contradicting short circuit load

[yefj]

Hello , As you can see in the simulation when we have a short load we have 0 impedance in the end because its 0 ohms.
On the other hand as you can see below in the simulation when we have inductive load then we have negative bump in the tdr.
A shorting via can ve viewed as inductor because its a straight line .
Why in our EM simulation I dont have negative bump as in the LTspice simulation?
Thanks.

 

[Baluncore]

You really make it difficult on yourself by using lumped element transition lines instead of the wide bandwidth TLINE model available in LTspice.

Your EM simulation has a filter in the transmission line, that appears to be missing from the LTspice lumped TLINE models.

Your lumped line has a sharp cutoff frequency that makes it difficult to see things at the far end. With TDR, I expect a positive kick from an inductive load, but followed by a low impedance. I expect a negative kick from a terminal capacitor, followed by a high impedance. All of that is hidden by the Gibbs effect of the sharp frequency cutoff, of your short lumped lines.

You get less help, and waste our time, when you do not attach the LTspice .asc and .plt files.

 

[yefj]

Hello Baluncore, Sorry yes I understand.
As you can see I simplified the model into one microstrip line with short at the end .
From the power flow simulation the signal reaches the short at 0.44ns.
few questions:
1.As you can see in the CST TDR when the signal comes back from the short at around 1ns It creates small ripples at 1ns.why is it happening?
2.a short at the can have inductive properties and series resistive properties.
when Its more inductive then resistive then the behavior is gamma positive .
How can I asses based on the geometry of the short the effective inductance and series resistance of the load?
3.same thing with open load , It has its very large resistive properties but a small capacitative properties ,when the capacitative load gets too large then the behavior of the reflected signal reverses.
How can I asses based on the geometry of the open load the effective inductance and series resistance of the load?
4.I have made a LTspice simulation as shown in the photos below and in the attached files.
What is the intuition behind the shape of this inductive peak? why the echo from this kind of load is such a peak?

Thanks.

F

 

[Baluncore]

1.As you can see in the CST TDR when the signal comes back from the short at around 1ns It creates small ripples at 1ns. why is it happening?

Your via is an inductor, but if you have not trimmed the track where the via is located, it makes a small parallel plate capacitor in parallel with the inductive via. I believe the TDR step is ringing the resonance of that tank circuit.

2.a short at the can have inductive properties and series resistive properties.
when Its more inductive then resistive then the behavior is gamma positive .
How can I asses based on the geometry of the short the effective inductance and series resistance of the load?

If the kick is first positive, it is inductive. The final value of the TDR trace will be the series resistance.

3.same thing with open load , It has its very large resistive properties but a small capacitative properties ,when the capacitative load gets too large then the behavior of the reflected signal reverses.
How can I asses based on the geometry of the open load the effective inductance and series resistance of the load?

I guess you meant effective capacitive and series resistance.
If the kick is negative, then the load is capacitive. The series resistance of the capacitor determines the dv/dt of the kick, then at the end of the TDR, the trace will settle to the parallel resistance of the capacitor

4.I have made a LTspice simulation as shown in the photos below and in the attached files.
What is the intuition behind the shape of this inductive peak? why the echo from this kind of load is such a peak?

I believe the bandwidth is too low because your pulse rise time is 100ns. For such a short line I would use 1ns rise and fall times.

Current in an inductor cannot change instantly.
V = L * di/dt ; so, di/dt = V/L.
An inductor therefor looks at first to the step voltage, like an open circuit. Then at the end of the TDR trace, there remains only the low series resistance of the inductor.

 

[Baluncore]

Here I compare lumped lines with TLINE in LTspice.

I adjusted your lumped lines to have Zo = 50 ohms. I halved the end component lumps, which removed echos due to line mismatch.
The green trace shows a wideband line with an inductive termination.
The white trace shows a wideband line with a capacitive termination.
The red trace shows a lumped line with an inductive termination.
The yellow trace shows a lumped line with a capacitive termination.
All the ringing is Gibbs effect, due to the narrow bandwidth of the lumped lines when compared with the spectrum of the voltage step.

 

[yefj]

Hello Baluncore,Gibbs effect if I understand correctly is saying that when our bandwidth is limited in the transmission line then harmonic data gets filtered thus given us ripples(sinusoidal data).
I have built the Ltspice simulation shown below and attached the LTspice file.

few questions:
1 .Suppose I dont want to change the line in LTspice.Could you reccomend how to recreate this BW issue , how can I make the pulse BW higher then the BW of the line element in LTspice?
2.In real life or EM simulation the TL line can be represented as S2P file.
What is the BW of the microstrip TLline?
3.I know that the formula for pulse BW=0.35/Trise(10-90)
How can I know that the BW of my real world microstrip line is too little for the input pulse ?
4.What could cause such ringing in real life lab situation?Is the gibbs effect in real lab situation?
Thanks.

 

[Baluncore]

1 .Suppose I dont want to change the line in LTspice.how can you reccommend to recreate this BW issue , how can I make the pulse BW higher then the BW of the line element in LTspice?

The LTspice TLINE model has infinite BW, if that is what it needs. It effectively has a BW decided by the time step of the LTspice simulation. You can indirectly increase the BW by specifying very short rise times on the pulse generator.

To lower the BW of a TLINE, you insert a low-pass filter into the signal path, before or after the TLINE. You will then have a BW limited line.

To see the Gibbs effect, the LP filter must cut off the high frequencies, faster than the harmonics of the voltage step fall off. You should be able to simulate that with LTspice.

2.In real life or EM simulation the TL line can be represented as S2P file.
What is the BW of the microstrip TLline?

An S2P file specifies the real and imaginary components of phasors. Since a phasor cannot specify more than one cycle, TLines longer than one cycle cannot be specified.

3.I know that the formula for pulse BW=0.35/Trise(10-90)
How can I know that the BW of my real world microstrip line is too little for the input pulse ?

You will need to compute the cutoff frequency of the line. That will be related to the line separation from the ground plane, When a TEM wave, TE11, becomes too small to be supported in the coaxial cable, it is said to be cutoff.

4.What could cause such ringing in real life lab situation?Is the gibbs effect in real lab situation?

When you view a fast square wave with a slow oscilloscope in a real lab, you will see an oscillation begin to grow before it becomes the rising edge, followed after the transition by a similar dampened oscillation.

You can ask yourself how the earlier rising oscillation knew it was going to become the rising edge, prior to the rising edge. The explanation is that the signal shown on the screen of the oscilloscope has been delayed by many stages of vertical channel amplifiers, and possibly also by a delay line used to make a trigger event visible.

 

[yefj]

Hello Baluncore,I also assume that our short circuit VIA can be represented as LC structure and also cause a problem as shown below in the photo and attached LTspice simulation .
Which can also create ringing in TDR.As shown in the photo 66ps ringing period is 15GHz which is very close to the cuttoff frequency of the LC filter .
Also LC resonant frequency is the same as LC filter cuttoff frequency.
So I am trying to connect the logic between several terms:
few questions:
1.resonance has general theory definitions which is not helping me understand the situation .
Resonance is when we have standing waves and when magnetic energy turns into electric and vice versa.
Why pratically in resonance we see voltage oscilating ringing in the TDR?

2. Why cuttof frequency of the LC filter is the same as resonance frequency.

3.If we have regular filter responce then on the output we see destorted pulse.
However in the TDR we can see this output "filtered" waveform data travels back to the source.
Its intresting how whole oscilating filtered pulse data goes back to the source as reflection,why is that?
Thanks.

 

[Baluncore]

2. Why cuttof frequency of the LC filter is the same as resonance frequency.

It is not resonance. It is the spectrum of the voltage step with higher harmonics removed by the low-pass filter.

The highest harmonic present will be the highest one that passes the LP filter. The lowest harmonic missing, will be the one above the LP filter. That one will also have the greatest amplitude of all those remaining.

The step becomes progressively steeper, with sharper corners, as more harmonics are included. Take a look at the plots shown here:
https://en.wikipedia.org/wiki/Gibbs_phenomenon#Description
And here:
https://en.wikipedia.org/wiki/Gibbs_phenomenon#Square_wave_analysis