Interpretation of a memristor's hysterisis loop

In summary, the memristor has a hysteresis loop that decreases in area with increased frequency, and has a slight deformity at higher voltage values.
  • #1
madaari
5
0
Hi forums,
Following is the hysteresis loop of a standard memristor:
attachment.png

Please note that, the red one is for lowest frequency and black for highest frequency.

From the graph, one can take the following observations:
1> As frequency increases, area of graph decreases
2> With increase in frequency, graph tends to tilt more towards x axis
3> Slight deformity of the red curve at higher VI values.

I tried interpreting these observations, keeping in mind memristors Piecewise linear model(Is that a correct assumption?).

If second observation is correct:- Memristance decreases with increase in frequency and at frequency tending to infinity, it acts like a constant value resistance whose value should be Minimum possible value of memristance. Right?

Also, I need a bit explanation for observation number 3(about deformity). I'm unable to figure out it's reason.

Thanks,
[moderator edited out the OP's name and cross posting info.]
 

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  • #3
Yup, I had a look at it. I'm mostly comfortable with the physics, just had few questions about shape of hysteresis loop, the ones that i mentioned in my earlier post i couldn't correlate that to theory. Mainly, these two:

2> With increase in frequency, graph tends to tilt more towards x axis
3> Slight deformity of the red curve at higher VI values.

What's the reason of this tilt in 2? and deformity in 3?
 
  • #5
Ok, thanks. Skin effect could be a reason, i'll dig deeper into it.
 
  • #6
madaari said:
Ok, thanks. Skin effect could be a reason, i'll dig deeper into it.
But it's only skin deep :smile:
 
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  • #7
Ok, got one more strong argument for (3) observation i.e slight deformity at higher i-v values. In this paper:
M. D. Pickett, D. B. Strukov, J. L. Borghetti, J. J. Yang, G. S. Snider, D. R. Stewart, and R. S. Williams, “Switching Dynamics in Titanium Dioxide Memristive Devices,” J. Appl. Phys., vol. 106, p. 074508, 2009.

They explained the dominance of tunneling effect at higher voltages, which could lead to the observed slight deformity in memristor's i-v curve.
 
  • #8
madaari said:
Following is the hysteresis loop of a standard memristor:
attachment-png.png

I guess that these loops are calculated on base of the "memristor" model presented by Strukov et al. in their paper "The missing memristor found". If this is the case, there are no more physics in than a simple linear-drift model for mobile dopants.
 

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  • #9

1. What is a memristor's hysterisis loop?

A memristor's hysterisis loop is a graphical representation of the relationship between the voltage applied to the memristor and the resulting current. This loop shows the history of the memristor's behavior and demonstrates its ability to "remember" its previous states.

2. How is a memristor's hysterisis loop interpreted?

The shape of the loop can provide information about the memristor's resistance and the direction of current flow. The slope of the loop also indicates the memristor's sensitivity to changes in voltage.

3. What does it mean if a memristor's hysterisis loop is narrow?

A narrow hysterisis loop indicates that the memristor has a small range of resistance and is less sensitive to changes in voltage. This means that it will require a larger voltage to change its state, making it less efficient.

4. Can a memristor's hysterisis loop change over time?

Yes, a memristor's hysterisis loop can change over time due to factors such as aging, temperature, and voltage cycling. This can affect the memristor's performance and may require recalibration.

5. How is the information from a memristor's hysterisis loop used in applications?

The information from a memristor's hysterisis loop is used to design and optimize memristor-based circuits and devices. It can also be used to analyze and troubleshoot any issues with memristor performance.

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