Is Dynamic CMOS an Effective Method for Frequency Division?

  • Thread starter Thread starter jaus tail
  • Start date Start date
  • Tags Tags
    Cmos Frequency
AI Thread Summary
Dynamic CMOS circuits can produce output frequencies that match input frequencies, but understanding the logic table is crucial for accurate analysis. The discussion highlights the importance of multiple inputs and the retention of static charge in dynamic circuits, which can lead to open circuit outputs. Interview preparation is emphasized, with advice to focus on relevant topics and practical experiences, such as projects in Verilog. Participants share insights on common interview questions and the need to adapt knowledge from different areas, like Mathematica to Matlab. Overall, mastering dynamic CMOS logic and preparing for interviews are key takeaways.
jaus tail
Messages
613
Reaction score
48
Homework Statement
If input frequency is 4.35 GHz, what is output frequency
Relevant Equations
CMOS inverter theory. If Nmos has high gate voltage then Nmos conducts but if Pmos has high gate voltage, it turns off
245655

I made a table using excel as:
245656

D is output. Like this I get Output frequency is same as input frequency. But I'm not sure if this is correct.

PS: I'm aware I'm posting many questions, but I got interview exams coming up in August. Companies are going to come to university for recruitment and thus I'm brushing up my skills. Hope that's allowed...
 

Attachments

  • 1561450072909.png
    1561450072909.png
    11.9 KB · Views: 224
Physics news on Phys.org
You seem to be missing the multiple inputs to each stage:
A depends on F and on C, C depends on B and on F.

I think you need to work out what the logic table is for these two (A, C) before you work out your table for A, B, C, D.
 
  • Like
Likes jaus tail
You also need to note that this is a dynamic mos circuit, where gates can be neither high nor low (open circuit output) and the input to the next stage remains at its previous value, by retention of static charge on the gate.
 
  • Like
Likes jaus tail
For logic table A = not(C) * not(F) not means inverted. * means 'and' gate
B = not(A)
C = not(F)
Output = not(C)

What do 'gates be neither high nor low' mean?
 
Say C was high and F was low, then N1 and P2 are off. P1 is on, but in series with P2 which is off. So the output A is open circuit, not connected to high nor to low. So A does not alter the gates of P3, N2 and N3. They hold their existing state (temporarily) due to the capacitance of their gate.
So the logic rule you gave, A=Not(C) And Not(F) is not necessarily correct when C=1 and F=0.

I have not worked with this sort of circuit, so I can't really help with the correct approach. I simply note that this is not a simple static logic circuit. My own (very old) CMOS text doesn't seem to mention these circuits.
Presumably, since you're being asked to analyse (or recognise) this circuit, you have come across this before.
 
  • Like
Likes jaus tail
jaus tail said:
Problem Statement: If input frequency is 4.35 GHz, what is output frequency

...

PS: I'm aware I'm posting many questions, but I got interview exams coming up in August. Companies are going to come to university for recruitment and thus I'm brushing up my skills. Hope that's allowed...

Ask other students who’ve been through these interviews to see what kinds of questions they will ask. In the US, I seriously doubt they ask any kind of complex or detailed question rather ask about what you’ve studied, what areas you’d like to work in and what they have to offer. They would most likely take your resume and give you a call back or invite back for a more detailed interview if they’re interested.

I know in CS, there’s been a trend to ask odd questions to see how you'd might solve a particularly odd problem. Google was famous for those as well as Microsoft. I once had an interview where I was asked a C++ question which I had seen in a Dr Dobbs article on common interview questions.

I answered, mentioned the article and then asked another from it. The interviewer hadn’t heard of the article and couldn’t answer my question. I didn’t flunk him though, I just told him the answer and he was suitably impressed. Needless to say, I decided that wasn’t the company for me.
 
  • Like
Likes jaus tail
I haven't come across this circuit. We've come across questions like: advantage of cmos over transmission gates, draw cmos for nand gate and nor gate.
given a logical expression: AB + (C (A + B) ). Draw its CMOS configuration.

My resume has a verilog project. I put more focus on that subject, than on VLSI. :)

Thanks for the guidance and help. The question is very difficult and exhausting. I'll try to implement it in Cadence to find the waveform and frequency.
 
If you know you have some defficiency then you should learn enough to tak about it and if pressed honestly say your familiar with and don’t it would be too hard to learn with your experience.

As an example, they are interested in Matlab but you have Mathematica experience then you’d prep yourself on Matlab so you can talk intelligently about its features and then connect your experience to it saying while I don’t have a working knowledge of Matlab with my Mathematica experience it shouldn’t be too difficult to pick up.
 
  • Like
Likes jaus tail
Here's something on dynamic CMOS that I found recently and may be of interest to you:

http://www.eas.uccs.edu/~cwang/ECE5452_SOC/ECE5452_DynamicLogic.pdf
 
  • Like
Likes jaus tail
Back
Top