Digital circuit with D-flops and need to deal with asynchronous signal

[lostinxlation]

Suppose you design the digital circuit with D-flops and need to deal with asynchronous signals. Typical logic is receiving the async signal with a D flop followed by another D flop to deal with metastability. But how does double flopping benefit against the metastability ?

The first flop gets the async signal transitioning just around the rise edge of the clock, and this flop capatures the unknown state somewhere between 0 and 1. This propagates to the slave latch of the said flop on the fall edge of clock and goes out. The next flop captures this unknown state signal and pass it to its master latch... Eventually, doesn't this unknown state come out of slave latch of the 2nd flop ? If so, how does double flopping reduce the chance of metastability ?

 

[Cloudscape]

Series connection of flip flops allows the input signal to have 1 clock cycle to go to the stable 0 or 1 state.

 

[lostinxlation]

Series connection of flip flops allows the input signal to have 1 clock cycle to go to the stable 0 or 1 state.

That's what most of the books say, but that's what I don't get either.

If you have a combinational logic driven by a single flop and this flop goes into metastability, that metastable signal also has a whole cycle to settle, doesn't it ?
Once one of the flops goes into metastable condition, you can't predict when this settles and following logic, either flops or comb logic, would be affected by the metastable signal anyway. I don't don't get what difference double flop makes as opposed to a single flop followed by comb logic.

 

[es1]

I think this link explains it well.
http://www.asic-world.com/tidbits/metastablity.html

Basically if an input is async you cannot prevent the first flipflop from oscillating it's Q inside the cycle if that async edge hits the flipflop wrong (i.e. a timing violation). Assuming the flipflop is designed such that the oscillations will stop before the next synchronous edge of clock (usually a good assumption), the second flipflop blocks the oscillations from the first flipflop preventing it from propagating to the rest of the circuit.

 

[James S Saint]

I suspect you are worried about the improper data state being transferred from the first latch to the next and into the following circuitry. If I remember right from some 25 years ago, I got around that problem by using the clock signal to enable the data line into the first latch.

If you provide an AND gate prior to the latch to enable the data signal to the latch but allow that same clock to be the latch clock, data transitions cannot reach the latch until shortly after the prior clock edge. This prevents the metastate scenario from ever occurring.

The worst case data delay scenario is merely 99% of one clock. Double latches delay more or won't prevent the error depending on which arrangement you use.

I had to use that data enable method for one of NASA's common memory bank processors that had 64 somewhat randomly timed memory requests coming from 64 processors. It improved the performance of what they had been using.

 

[lostinxlation]

thanks.

I think I somehow understand how double flopping benefits.

Yes, the short answer is Let's give a full cycle to metastable state to settle like many books say. But I believe this simple statement should be accompanied by a little more details(which is lacking in many digital design books).

Assuming the receiving clock is running at 5ns cycle time. If you have double flops and the 1st flop goes into metastable state, it has 5ns to settle because of a flop to a flop connection. However, if you have a flop followed by comb logic which is, for example, 3ns deep before reaching the next sequential cells and this flop goes into metastable, the metastable state has virtually only 2ns to settle to avoid the weird state from getting captured by the next flop. This increases the chance that metastability not be resolved within a cycle and creates a big mess in the following blocks.

 

[es1]

lostinxlation, sounds like you understand it well enough and I think what you wrote is correct. The fact that the combinational logic reduces the required time to settle is why there is usually no logic in between the sync flipflops.

There is also another subtle problem though and this requires some understand of how the gates are actually made. Some flipflops don't oscillate their output but instead their Q sits at Vd/2 until it restabilizes.

Take a simple case where the gates are CMOS and the combo logic is just an inverter. If that inverter's input voltage is Vd/2 then it is likely sitting at a point where both it's top and bottom FET are conducting. This is very bad for power as the total resistance from Vd to Vs will be low, and if one stays in this state for too long then there is a possibility of burning out this gate ruining the circuit.

To avoid all these problems (the problem you mentioned and the problem I mentioned) people usually just don't put combinational logic between the flipflops. It makes it easier.