Suppose you design the digital circuit with D-flops and need to deal with asynchronous signals. Typical logic is receiving the async signal with a D flop followed by another D flop to deal with metastability. But how does double flopping benefit against the metastability ? The first flop gets the async signal transitioning just around the rise edge of the clock, and this flop capatures the unknown state somewhere between 0 and 1. This propagates to the slave latch of the said flop on the fall edge of clock and goes out. The next flop captures this unknown state signal and pass it to its master latch... Eventually, doesn't this unknown state come out of slave latch of the 2nd flop ? If so, how does double flopping reduce the chance of metastability ?