Electronic NOT gate chip question

  • #1
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Hi,

Can current flow both ways through a NOT gate, or is the diagram I saw, much like the picture I drew here, just drawn the wrong way around?
not.png

Anyway, say it was correct, so what does this mean? Because the chip itself (the not gate chip Vcc = 5V and Gnd) takes 5V between it and the chip ground. So when the 15V is active, pin 11 gets inverted to 0V? and When 15V is not active, what is pin 11? Is it then 5V? (So it is never 15V?)

For a larger context on what I'm trying to figure out:
1111111.PNG

It seems like the not gates and the LED and relay coil, are flowing backwards? Because Pin 9 of the flip flop is Q.
How does the current flow to or from pin 9? If pin 9 is high because it was pulsed with data on the clock then presumably pin 9 is 5V? (from Pin 12 and pin 10)? But 5V with reference to what ground?

Where the chip is:
92111-74HC74-D-type-Flip-Flop-Pic002-700x700.GIF

Thanks!
(I can provide more info on the diagram if needed)
 

Answers and Replies

  • #2
berkeman
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It is a design error to pull the output of a logic gate above its power supply. That can lead to latch-up of the gate, destroying it (with smoke usually)...
 
  • #3
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This is not a design error. The 7406 is a open-collector gate. And that means that 7406 can only sink current.
 
  • #4
berkeman
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This is not a design error. The 7406 is a open-collector gate. And that means that 7406 can only sink current.
Oops, I didn't check that. Thanks for the correction! :smile:

Can it handle 24V, though? And that coil drive without a flyback protection diode looks to be a problem...
 
  • #6
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Looks like the 7406 can handle 30V at its output. Still, the coil drive without the catch diode looks to be a problem.

http://www.ti.com.cn/cn/lit/ds/symlink/sn7406.pdf
I think the bottom relay had a flyback protection diode, that would look like this wouldn't it:
upload_2016-6-9_1-52-15.png

I don't know why the other two didn't...

What do you mean it can only sink current? So is anything flowing from the 15V or not? And what does this mean for Q when it is high?

Cheers
 
  • #7
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The 74HC74 is a CMOS version, the the output is build using only cmos invertter. And at first glance you can treat it as ideal switch with some resistance.
And the switch can connect Q to Vcc or to GND.
6.jpg


And now if we get CMOS inverter (NOT) gate and connect input node to positive terminal of a power supply.
So we have input at "high," or in a binary "1" state and the output is in "low" state or binary "0".
15.png

So output of a gate is now "sink" the current to provide a "0" or "low" state at the output. Vout is almost equal GND.

And now see what happens if we reverse the input's logic level to a binary "0", "low".
The output now must be in "High" binary "1" state. So output of a gate is "sourcing" the output current. And output voltage is almost equal VDD.
15b.png
 
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  • #8
berkeman
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What do you mean it can only sink current? So is anything flowing from the 15V or not? And what does this mean for Q when it is high?
Do you know what the output stage of an open-collector gate looks like? Check out the 7406 datasheet "schematic" for more info.
 
  • #9
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Thanks for the great replies!
The 74HC74 is a CMOS version, the the output is build using only cmos invertter. And at first glance you can treat it as ideal switch with some resistance.
And the switch can connect Q to Vcc or to GND.
View attachment 101813

And now if we get CMOS inverter (NOT) gate and connect input node to positive terminal of a power supply.
So we have input at "high," or in a binary "1" state and the output is in "low" state or binary "0".
View attachment 101814
So output of a gate is now "sink" the current to provide a "0" or "low" state at the output. Vout is almost equal GND.

And now see what happens if we reverse the input's logic level to a binary "0", "low".
The output now must be in "High" binary "1" state. So output of a gate is "sourcing" the output current. And output voltage is almost equal VDD.
View attachment 101815
Okay, so that means that Q is either 5V as supplied by Vcc (not pin 12) or zero, as supplied by Gnd.
I'm still struggling to come to terms with the NOT gate. So this means that the back end of the not gate is acting like a switch to, for instance, make pin 9, when Q is 5V, (become inverted to zero volts) sinking the 15V to Gnd and make the LED turn on? And make Pin 4 (of that NOT gate) sink the 24V and turn on the relay?

Do you know what the output stage of an open-collector gate looks like? Check out the 7406 datasheet "schematic" for more info.
I'll look that up in the morning, it's almost 3am here.

Thanks!

P.S. So what did the flyback diode (as highlighted in #6) do? (Why is it necessary?)
 
  • #10
berkeman
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So what did the flyback diode (as highlighted in #6) do? (Why is it necessary?)
Without it, when the pulldown transistor in the drive gate opens up (to turn off the coil current), you get a large positive voltage spike at the bottom of the inductor, which can blow up the output transistor.

https://en.wikipedia.org/wiki/Flyback_diode
 
  • #11
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Okay, so that means that Q is either 5V as supplied by Vcc (not pin 12) or zero, as supplied by Gnd.
Yes, Q can be at 5V (almost, load dependent) supplied by Vcc/Vdd (pin 14). And Q can be 0V also (supplied by Gnd pin 8)

I'm still struggling to come to terms with the NOT gate. So this means that the back end of the not gate is acting like a switch to, for instance, make pin 9, when Q is 5V, (become inverted to zero volts) sinking the 15V to Gnd and make the LED turn on? And make Pin 4 (of that NOT gate) sink the 24V and turn on the relay
Normally the inputs are "voltage driven", almost no input current is needed for CMOS (I_IL = 1.6mA ; I_IH = 0.04mA max for TTL gates ).
So, when the pin 9 is at +5V (high state) the inverter (NOT gate) will open his BJT at the output (the output is short via saturated transistor to pin 8/GND). The "output switch" can only short to GND in "open-collector gates". Therefore the current from +15V will start to flow :
+15V----->Resistor---LED----> pin 10 (NPN transistor)----> pin 8 ----> -15V (GND). And we have the same situation the the relay. But this time the current is supplied by 24V source.
 
  • #12
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I don't think I've ever had such a succinctly helpful post before.
Without it, when the pulldown transistor in the drive gate opens up (to turn off the coil current), you get a large positive voltage spike at the bottom of the inductor, which can blow up the output transistor.

https://en.wikipedia.org/wiki/Flyback_diode
Yes, that is something to consider, I suppose I just didn't expect that even such tiny silicon switches and small relay coils deserve the same treatment as large inductors.

Normally the inputs are "voltage driven", almost no input current is needed for CMOS (I_IL = 1.6mA ; I_IH = 0.04mA max for TTL gates ).
So, when the pin 9 is at +5V (high state) the inverter (NOT gate) will open his BJT at the output (the output is short via saturated transistor to pin 8/GND). The "output switch" can only short to GND in "open-collector gates". Therefore the current from +15V will start to flow :
+15V----->Resistor---LED----> pin 10 (NPN transistor)----> pin 8 ----> -15V (GND). And we have the same situation the the relay. But this time the current is supplied by 24V source.
Interesting about the CMOS.
Brilliant reply, and I'm so close to fully grappling with it. But I have a couple questions, (I looked up Open Collector on wiki) so are you saying that in the state pictures for #7, there is a PNP BJT at the output that isn't seen?
what do you mean -15V? Isn't it just +15V and zero V for GND?
I was thinking so pin 9 is ~ 5V, it'd be:
+15V----->Resistor---LED---->Pin 10 ----> Pin 7 GND (so GND is pin 7 of the 'NOT chip', not seen in our diagram)
What was the pin 8 you were talking about?

Thanks heaps
 
  • #13
davenn
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Brilliant reply, and I'm so close to fully grappling with it. But I have a couple questions, (I looked up Open Collector on wiki) so are you saying that in the state pictures for #7, there is a PNP BJT at the output that isn't seen?
no, as can be seen, there is a P channel and a N channel MOSFET on the output ( because these are CMOS examples )


If they were standard TTL then it would have BJT transistor outputs
look at the diagrams on this page .,.. easier than me explaining it :)

http://www.radio-electronics.com/in...-ic-families-technologies/7400-series-ttl.php


Dave
 
  • #15
davenn
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I didn't think so, what did Jony123 mean by BJT and PNP then?
presumably you were referring to this ......

Normally the inputs are "voltage driven", almost no input current is needed for CMOS (I_IL = 1.6mA ; I_IH = 0.04mA max for TTL gates ).
So, when the pin 9 is at +5V (high state) the inverter (NOT gate) will open his BJT at the output (the output is short via saturated transistor to pin 8/GND). The "output switch" can only short to GND in "open-collector gates". Therefore the current from +15V will start to flow :
+15V----->Resistor---LED----> pin 10 (NPN transistor)----> pin 8 ----> -15V (GND). And we have the same situation the the relay. But this time the current is supplied by 24V source.
the bit bolded is a little confusing as he is referring to CMOS and TTL in the same sentence but the rest of the comments
should be referring to a TTL output

hopefully he will return and clarify his comments :smile:


Dave
 
  • #16
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presumably you were referring to this ......



the bit bolded is a little confusing as he is referring to CMOS and TTL in the same sentence but the rest of the comments
should be referring to a TTL output

hopefully he will return and clarify his comments :smile:


Dave
Sort of, I was also thinking of:
will open his BJT at the output (the output is short via saturated transistor to pin 8/GND). The "output switch" can only short to GND in "open-collector gates". Therefore the current from +15V will start to flow :
+15V----->Resistor---LED----> pin 10 (NPN transistor)
Indeed.



Cheers!
 
  • #17
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so are you saying that in the state pictures for #7, there is a PNP BJT at the output that isn't seen?
Sorry for confusing you. Post #7 shows CMOS gate 74HC/74HCT family or CD4000 family. And in CMOS we have a P-Channel MOSFET (the upper one ) and N-Channel MOSFET (lower transistor). The NOT gate (7406) is TTL circuit - Transistor-Transistor-Logic (BJT only).

what do you mean -15V?
Negative terminal of a 15 supply

+15V----->Resistor---LED---->Pin 10 ----> Pin 7 GND (so GND is pin 7 of the 'NOT chip', not seen in our diagram)
Very good. And we draw a circuit that contains an logic circuit or a opamp we very often skip the power supply on the diagram to make the circuit more easy to analysis. But we have to kept in mind that every circuit needs a power supply.

What was the pin 8 you were talking about?
My mistake, I meant pin 7.
 
  • #18
davenn
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Negative terminal of a 15 supply
just be careful with your terminology in future :wink:
as -15V is a negative 15V rail of a split rail PSU, which is very different to a 0V rail of a single rail PSU


Dave
 
  • #19
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My mistake, I meant pin 7.
Yeah I think I understand, because they're all (all the ICs) fed by the same positive rail and grounded by the same earth, we can omit them somewhat in the digram.

Negative terminal of a 15 supply
just be careful with your terminology in future :wink:
as -15V is a negative 15V rail of a split rail PSU, which is very different to a 0V rail of a single rail PSU
Wait, so is -15v the same as 0v? Or not?
It's Ground right?
Because I would think that +15V to -15V is a 30V potential...
I didn't remember a -15V rail in the diagram.

Thanks
 
  • #20
davenn
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Yeah I think I understand, because they're all (all the ICs) fed by the same positive rail and grounded by the same earth, we can omit them somewhat in the digram.



Wait, so is -15v the same as 0v? Or not?
It's Ground right?
Because I would think that +15V to -15V is a 30V potential...
I didn't remember a -15V rail in the diagram.

Thanks
again jony130 was a bit unclear
In this case he really meant the 0V / negative terminal of the PSU, NOT -15V
This is why I was telling him to be careful with his terminology so as to avoid the sort of confusion that resulted in the above posts

It's Ground right?
no, it's just 0V ..... ground (GND) refers to a different situation where the 0V rail is connected say to the metal chassis which may or may not be connected to a physical ground via the mains or other cabling. There was a thread on here some time ago discussing the various types of grounds, the misuse of the term etc



Dave
 
  • #21
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no, it's just 0V ..... ground (GND) refers to a different situation where the 0V rail is connected say to the metal chassis which may or may not be connected to a physical ground via the mains or other cabling. There was a thread on here some time ago discussing the various types of grounds, the misuse of the term etc
In "modern" electronics we can have a ground without any metal chassis. Simply, the ground is a reference point in respect of which we are measure all voltage in the circuit. And if a Negative terminal (PSU) is used as a our reference point, we can declare this point as a ground. But I'm sure you already know this.
To measure the voltage we need two point in the space. One of this point is treat as a reference point. We have a very similarity situation when we try to measure a height of an object. We need a reference point. The most common reference pint is "above mean sea level". But when you measure the height of the table in your house the floor now becomes your reference point.
0.1.PNG
 
  • #22
davenn
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In "modern" electronics we can have a ground without any metal chassis. Simply, the ground is a reference point in respect of which we are measure all voltage in the circuit. And if a Negative terminal (PSU) is used as a our reference point, we can declare this point as a ground. But I'm sure you already know this.
and that is exactly what I was commenting on as a misuse of the term :smile:
It;s just the point you are going to make as your reference but to which all other points of potential ( positive or negative to that reference) are referred back to


D
 
  • #23
berkeman
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Yeah, in an offline switch-mode power supply product I'm working on right now, we have at least three "grounds" that we keep track of. Two on the primary side labeled PGND and NGND, and one on the secondary side labeled ISOGND. At the moment, we are not connecting the external Earth ground to any of these internal ground nets. Each ground symbol in our schematic is labeled so that we can keep track of things... :smile:
 
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  • #24
davenn
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Two on the primary side labeled PGND and NGND, and one on the secondary side labeled ISOGND.

and you don't have a digital ground as well ?? haha :wink:
 
  • #25
berkeman
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and you don't have a digital ground as well ?? haha :wink:
No but we do have a couple of bead-isolated analog supplies on both sides of the isolation barrier. Always watching out for shared impedance noise. :smile: Thanks brother.
 

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