Lead/Lag compensator - lead and lag time to pole and zero locations

  1. Hi,

    I am having difficulty understanding how to convert pole and zero locations of a lead lag compensator into lead and lag time and vise versa.

    I have a digital lead and lag compensator which requests: gain, lead time (min) and lag time (min). However i have the gain zeros and poles of the compensator.

    If someone can tell me how to do this i would be most grateful.

  2. jcsd
  3. berkeman

    Staff: Mentor

    Given the DC gain and poles and zeros of the transfer function, you should be able to make a Bode Plot that will show you your gain and phase margin. A pole gives you lead, and a zero gives you lag. You can adjust the position of the poles and zeros to ensure that you have adequate phase margin to ensure stability.


    Although I notice that the concept of lead-lag compensation may be treated a bit differently in control theory, compared to the circuit design context that I'm familiar with:


    Hope that helps.
  4. yes i know that you can draw a bode plot from it to get the phase and gain margins but my specs are in the time domain so I have it in transfer function form like K.(s+zd)(s+zg)/(s+pd)(s+pg) where d is for lead and g is for lag. I don't understand how I can get this lag or lead time from either the bode plot or the root locus.
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