Logisim question -- Simulation of a small logic circuit is not working

[peripatein]

I am trying to implement the following circuit in Logisim, yet all I get is y=0. Any idea what might be the problem? First image is what I am trying to implement; second it my Logisim attempt which yields 0. I'd appreciate some feedback.

 

[lewando]

I don't see a problem. Assuming your D-flops start out in state Q = 0, Y = 0 is the correct output for this circuit whether X = 0 or X = 1. What were you expecting this circuit to do?

 

[Baluncore]

Your D-F/F inputs are all driven by outputs of F/Fs.
If all F/Fs start with zero, how can you ever get a 1 to break the tradition?

 

[peripatein]

Your D-F/F inputs are all driven by outputs of F/Fs.
If all F/Fs start with zero, how can you ever get a 1 to break the tradition?

That's precisely my problem! How do I set the initial state? How do I assign the initial state to the DFFs? This is my very first attempt at designing something synchronous using Logisim and DFFs; could you please guide me through fixing these issues stymieing it from working properly?
I was asked to include a reset button which would initialize the DFFs but how should that be connected? Should I connect a reset to the Preset or Clear of the DFFs?

 

[peripatein]

I don't see a problem. Assuming your D-flops start out in state Q = 0, Y = 0 is the correct output for this circuit whether X = 0 or X = 1. What were you expecting this circuit to do?

Lewando, how do I set the initial state? How do I assign the initial state to the DFFs? Could you please guide me through?

 

[Baluncore]

state Q2 Q1 Q0 initial state of F/Fs.
selx0 Q1 Q2 Q0 when clocked, swaps the two bits on the LHS.
selx1 Q2 Q0 Q1 when clocked, swaps the two bits on the RHS.

So the number of ones or zeros remains the same when clocked.
If state is 000 then it stays 000. If state is 111 then it stays 111.

If initial state has a single 1, state can only cycle through 001, 010 and 100.
If initial state has a single 0, state can only cycle through 110, 101 and 011.

The initial state, and how you reach it depends entirely on the application of this state machine.

 

[peripatein]

state Q2 Q1 Q0 initial state of F/Fs.
selx0 Q1 Q2 Q0 when clocked, swaps the two bits on the LHS.
selx1 Q2 Q0 Q1 when clocked, swaps the two bits on the RHS.

So the number of ones or zeros remains the same when clocked.
If state is 000 then it stays 000. If state is 111 then it stays 111.

If initial state has a single 1, state can only cycle through 001, 010 and 100.
If initial state has a single 0, state can only cycle through 110, 101 and 011.

The initial state, and how you reach it depends entirely on the application of this state machine.

I am still not sure I understand. It's expected to be the implementation of the FSM found here:
http://www.cs.unca.edu/~bruce/Fall10/255L/Lab5FSM.html
This FSM outputs the quotient of x/3. I know that the implementation is correct I simply don't know how to initialize it in Logisim.

 

[Baluncore]

As I understand it, you will clock THREE bits of data sequentially into a TWO bit state machine register that holds the Mod 3 remainder. If your implementation was correct then it would follow the state diagram shown in “Part 2: Your FSM”. You should revisit the state diagram and fill in the truth table so we can see what you are simulating.

 

[Baluncore]

Each time you shift the next bit in, you change the mod 3 remainder in a fixed pattern because the shift doubles the value and adds one if the input was one.

   current      next if 0    next if 1
   N   N mod 3   2N mod 3    2N+1 mod 3
    0    0       0    0       1    1
    1    1       2    2       3    0
    2    2       4    1       5    2
    3    0       6    0       7    1
    4    1       8    2       9    0
    5    2      10    1      11    2
    6    0      12    0      13    1
    7    1      14    2      15    0
    8    2      16    1      17    2
    9    0      18    0      19    1
   10    1      20    2      21    0
   11    2      22    1      23    2
   12    0      24    0      25    1
   13    1      26    2      27    0
   14    2      28    1      29    2
   15    0      30    0      31    1
   16    1      32    2      33    0
   17    2      34    1      35    2
   18    0      36    0      37    1
   19    1      38    2      39    0
   20    2      40    1      41    2

 

[peripatein]

Perhaps this will help. It's certainly relevant and relates directly to the implementation.
001 is the first state (remainder 0), 010 is the second state (remainder 1), 100 is the third state (remainder 2).
What I truly need help with is the Logisim implementation. How do I initiate the system? How do I assign the proper values to the DFFs so it starts from 001?

 

[Baluncore]

What I truly need help with is the Logisim implementation. How do I initiate the system? How do I assign the proper values to the DFFs so it starts from 001?

It does not start at state 001, it starts at state 00.
You are using three D-F/Fs to store three states. 0, 1 and 2.
But you only need two D-F/Fs to store the current state in binary. State = 00, 01 or 10.
The two bits of the current state and the one input bit gives three terms that will be used to determine the next two bit state, the new remainder. The first state will be 00.

 

[peripatein]

It does not start at state 001, it starts at state 00.
You are using three D-F/Fs to store three states. 0, 1 and 2.
But you only need two D-F/Fs to store the current state in binary. State = 00, 01 or 10.
The two bits of the current state and the one input bit gives three terms that will be used to determine the next two bit state, the new remainder. The first state will be 00.

You didn't fully read my comment. "001 is the first state (remainder 0), 010 is the second state (remainder 1), 100 is the third state (remainder 2)." It's merely a notation; obviously the first state is 00, second is 01, third is 10, according to the remainder, but this is merely a notation. Replace 001 with 00, 010 with 01, and 100 with 10 and the two notations are perfectly synched. Again, what I need help with is how to initialize it in Logisim. Could you please help?

 

[Baluncore]

At the bottom of the D-F/F there are three terminals. Set to one, enable and clear to zero. Use those to set the initial state. You will need to create a reset pulse.

The Set input is not needed if you use two D-F/Fs to hold the state. Then the serial input bit provides the 1 for the 01 state.
If there were 16 states in the engine, would you use 16x D-F/Fs, or just 4x D-F/Fs ?

 

[peripatein]

At the bottom of the D-F/F there are three terminals. Set to one, enable and clear to zero. Use those to set the initial state. You will need to create a reset pulse.

The Set input is not needed if you use two D-F/Fs to hold the state. Then the serial input bit provides the 1 for the 01 state.
If there were 16 states in the engine, would you use 16x D-F/Fs, or just 4x D-F/Fs ?

Let's see whether I understand. I create a reset pulse and connect it to the state 00. I also connect the input to the 01 state. I connect a constant '1' to all the Enable's? Is that correct (assuming it's not :-))? Re your question, I would probably use only 4 as I could switch between the different states and won't need per se a F/F for each state.

 

[Baluncore]

Let's see whether I understand. I create a reset pulse and connect it to the state 00.

At the start you reset the state machine to the initial state. You do that by setting state 0.

I also connect the input to the 01 state.

There are too many interpretations of that sentence, I do not understand what you mean. Connect the input to the input or the output of state or F/F?

I connect a constant '1' to all the Enable's?

At some point you will need to use the help file and experiment with simple test logic. You will then know the answer to that question. How come F/Fs worked before you found the extra controls?

Re your question, I would probably use only 4 as I could switch between the different states and won't need per se a F/F for each state.

Then why do you use three for this project, when the state diagram and the current state logic table clearly shows only two being used? This is after all, an exercise in state machines, not ring counters or bi-directional shift registers. It is also a basic introduction to serial arithmetic of long binary numbers.