Need Help Understanding a Problem About CPUs

[olen501]

Homework Statement

This is the problem:

Consider a CPU that has a clock cycle of 20 nanoseconds (ns). It is possible to remove some instructions from its assembly language instruction set to form a second CPU and reduce its clock cycle to 18 ns. These instructions comprise 4 percent of all code in a typical assembly language program, and each of these removed instructions would have to be replaced by 3 instructions from the reduced set. Assume that every instruction requires the same number of clock cycles, c, to complete (i.e., to be fetched, decoded, and executed with results written back).
(a.)
Which CPU has the better performance?
(b.)
What percentage of typical code would the removed instructions have to comprise in order for the two CPUs to have the same performance?
(c.)
For what clock cycle for the original CPU would the two CPUs have the same performance?

Homework Equations

T = (N*S)/R

N = actual number of instructions
executed in program
S = average number of cycles for
instructions in program
R = clock rate
T = program execution time

The Attempt at a Solution

I actually don't need help solving the problem (not yet anyways).
My problem is that to me it seems this problem is worded kind of
poorly and I don't really understand what it's trying to say about
the new instructions comprising 4 percent of the code and the
removed instructions being replaced by 3 instructions from the
reduced set. Can someone explain this problem to me?

 

[NateTG]

I actually don't need help solving the problem (not yet anyways).
My problem is that to me it seems this problem is worded kind of
poorly and I don't really understand what it's trying to say about
the new instructions comprising 4 percent of the code and the
removed instructions being replaced by 3 instructions from the
reduced set. Can someone explain this problem to me?

Let's say that there are instructions A-Y and performing instructions BCD in order will do the same thing as instruction A will do by itself. Now, you have the choice between a chip that will do all of A-Y in 20 ns each, or one that will do B-Y (so you have to replace all the A's with BCD) in 18 ns each.

 

[olen501]

Thanks for the help, I've got it now