NOT logic at transistor/componet level

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Discussion Overview

The discussion revolves around the understanding of NOT logic at the transistor/component level, particularly focusing on the behavior of transistors in a TTL inverter circuit. Participants explore the implications of current flow, voltage levels, and the roles of various components in the circuit.

Discussion Character

  • Technical explanation
  • Debate/contested
  • Mathematical reasoning

Main Points Raised

  • Some participants question the representation of current flow in diagrams, particularly regarding the direction of arrows and whether they indicate electron flow or conventional current.
  • There is uncertainty about the role of certain components, such as diodes D1 and D2, with participants discussing their necessity and function within the circuit.
  • Participants explore the behavior of transistors in different biasing conditions, including the implications of Q1 being in cut-off and Q2 being in saturation.
  • Some participants propose that the base current can flow in a specific path due to the configuration of the transistors, while others challenge this understanding.
  • There is a discussion about the impact of D2 on the operation of Q3, with some arguing that without D2, Q3 would turn on and waste current.
  • Concerns are raised about the concept of fan-out and its relevance to the circuit's performance, with some participants expressing a lack of familiarity with the term.

Areas of Agreement / Disagreement

Participants express differing views on the interpretation of current flow and the necessity of certain components in the circuit. There is no clear consensus on the implications of these components or the overall understanding of the circuit's behavior.

Contextual Notes

Participants reference specific voltage levels and conditions under which transistors operate, but there are unresolved assumptions regarding the definitions of terms and the implications of circuit configurations.

Who May Find This Useful

This discussion may be useful for individuals interested in transistor logic circuits, particularly those studying TTL inverters and the nuances of current flow and component interactions in digital electronics.

xconwing
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Hello all,

Reading this article
http://www.allaboutcircuits.com/vol_4/chpt_3/2.html
explaining NOT logic at component level.

I'm not sure I understanding the arrow drawn in this figure: above sentence "This tells us that ..."
04165.png


Is the arrow depicted current? If so, would that make passing the 5 V on the right as a "lost" of 5 V?
Why Q3 was not included in this picture?

Initial diagram:
04074.png
 
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Those arrows are crazy! Is he trying to plot electron flow? Bizzare...

Ignoring everything after the first figure with the real schematic, do you see how that TTL inverter works? If not, just post the schematic pic and we can talk through it.
 
to berkeman:
No, I still don't understand, the schematic that is. That is weird if they want to bring up the electron flows direction.

quick question:
a) A diode in reverse bias is treated as an open?
b) No voltage to the base of transistor is open at collector node?
 
xconwing said:
quick question:
a) A diode in reverse bias is treated as an open?
b) No voltage to the base of transistor is open at collector node?
yes and yes
 
@ the initial diagram:
1) where the box with "0 V", why is that zero volt, should that be Vcc?
2) can current travel from Vcc through R1 out of Q1 collector and into Q2 base? I thought current through transistor is unidirectional, from collector to emitter.
 
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xconwing said:
@ the initial diagram:
1) where the box with "0 V", why is that zero volt, should that be Vcc?
The box apparently represents a multimeter; it is recording 0v between the base (connected directly to Vcc) and the Vcc bus. Let's call that box a DVM. :smile:

Q3 is not involved here because it takes no part when input is HIGH. In this state, Q3 is deprived of base drive so Q3 is off.

xconwing said:
2) can current travel from Vcc through R1 out of Q1 collector and into Q2 base? I thought current through transistor is unidirectional, from collector to emitter.

Yes, current flows wherever KVL says it can. :smile:

B-C is a PN junction, just like a diode, so if it's forward biased it will conduct. When a transistor is used as a linear amplifier then B-C junction is kept reverse-biased, but in digital circuits the transistor characteristics can be exploited even more creatively. :wink:
 
xconwing said:
I'm not sure I understanding the arrow drawn in this figure: above sentence "This tells us that ..."
HI, first you must know that allaboutcircuits textbook use a electron flow not conventional flow.
http://www.allaboutcircuits.com/vol_1/chpt_1/7.html
And this is why the arrows in the diagram pointing in the opposite direction.
Next notice that Q1 is a NPN transistor and his emitter is connected to Vcc. The base is also pull up to Vcc via R1 resistor. Therefore the base-emitter junction is reversed biased. So in normal situation Q1will be in cut-off region. But in this case Q1 collector is directly connected to Q2 base. And this change the situation completely.Can we find a closed path for Q1 base current from Vcc to GND?
Yes we can. The base current can flow from Vcc--->R1--->Q1 Base -collector junction---->Q2 Base-emitter junction--->GND. Notice that Q1 base collector junction is now forward biased, and the is why the current can flow.
So in this scenario Q1 is working in inverse mode also know as a reverse active region.
xconwing said:
Why Q3 was not included in this picture?
Please notice that Q2 is in saturation region due to Q1 base-collector current. So what is happening here is that the current through R2 splits between Q1 collector current and the Q3 base current. The more current that is allowed to go through Q2 transistor ( Q2 in saturation), the less current that will go into the Q3 base.
So Q2 simply steals all the Q3 base current ans this is why Q3 is cut-off.
 
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When input is 1 (Vcc), Q1(B-C),Q2(B-E) and Q4(B-E) act as forward biased diodes. Since BE junction of Q2 is forward biased, CE voltage will drop to a very small
arrow-10x10.png
value (equivalent to logic 0). Thus, voltage at the base of Q3 is also 0. So,Q3 is open circuited along with the D2 diode. That means base and collector of Q4 are at the same potential ,approximately 0.7 volts w.r.t ground, equivalent to logic 0. So, output CE voltage is low.
When input is 0, Q1 will conduct, this will pull down voltage level at the base of Q2, turning it off. So, voltage at collector of Q2 will be high (logic 1). Meanwhile, Q2 being off, base of Q4 will be pulled down to ground potential. So, Q4 will be off. Vcc will reach to collector of Q4 through forward biased Q3 and D2. So,CE voltage of Q4 is Vcc i.e logic 1.
If my understanding is right, I don't understand the purpose of D1 and D2 diodes, because without them too, the circuit will work as above. Am I missing something?
 
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cnh1995 said:
If my understanding is right, I don't understand the purpose of D1 and D2 diodes, because without them too, the circuit will work as above. Am I missing something?
D1 is just a protection diode.
D2 diode has a very important task. But first let as check the situation when input is "high" (1).
What is the voltage level at Q3 base?? Are you sure that this voltage is 0 ?
Q3 base voltage must be equal to VbeQ4 plus Q2 saturation voltage.
Vb3 = Vbe4 + Vce2sat = 0.6V + 0.2V = 0.8V . You are surprised ? How can Q3 be OFF if Q3 base voltage is 0.8V ??
For sure without D2 diode Q3 transistor would have been turned on.
And this is why designers add D2 into the circuit. To make sure that Q3 will be OFF when Q2 is saturated.
 
  • #10
Jony130 said:
D1 is just a protection diode.
D2 diode has a very important task. But first let as check the situation when input is "high" (1).
What is the voltage level at Q3 base?? Are you sure that this voltage is 0 ?
Q3 base voltage must be equal to VbeQ4 plus Q2 saturation voltage.
Vb3 = Vbe4 + Vce2sat = 0.6V + 0.2V = 0.8V . You are surprised ? How can Q3 be OFF if Q3 base voltage is 0.8V ??
For sure without D2 diode Q3 transistor would have been turned on.
And this is why designers add D2 into the circuit. To make sure that Q3 will be OFF when Q2 is saturated.
Yeah..But if D2 weren't there, Q3 would turn on and conduct. But Q4 is already on with Vbe4=0.6 volts.That means collector current of Q4 will now pass through D2 and Q3,and a little base current through Q4 base. Still the output Vce4sat would be small enough (about 0.2V) i.e. logic 0.
 
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  • #11
cnh1995 said:
But if D2 weren't there, Q3 would turn on and conduct.
And that will be a waste of current, it achieves nothing useful and reduces the fan-out of Q4. We'd like all of the current through Q4 to be from the input stages of the gates that Q4 drives to maximize this gate's fan-out.
 
  • #12
NascentOxygen said:
And that will be a waste of current, it achieves nothing useful and reduces the fan-out of Q4. We'd like all of the current through Q4 to be from the input stages of the gates that Q4 drives to maximize this gate's fan-out.
Okay..I am not familiar with the concept of fan-out you are talking about...Gotta study that:smile: Thanks a lot..
 
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  • #13
cnh1995 said:
Yeah..But if D2 weren't there, Q3 would turn on and conduct. But Q4 is already on with Vbe4=0.6 volts.That means collector current of Q4 will now pass through D2 and Q3,and a little base current through Q4 base. Still the output Vce4sat would be small enough (about 0.2V) i.e. logic 0.
Well yes, but by doing this you are wasting a lot of current. Also without the load we have Ic3 = Ic4 so Vce_sat voltage will also increase his value and this will decrease the noise margin
http://www.allaboutcircuits.com/vol_4/chpt_3/10.html
Also notice that now Q4 can sink much smaller current from the load because know Ic4 = Iload + Ic3 before Q4 starts leaving the saturation region.
 
  • #14
Jony130 said:
Well yes, but by doing this you are wasting a lot of current. Also without the load we have Ic3 = Ic4 so Vce_sat voltage will also increase his value and this will decrease the noise margin
http://www.allaboutcircuits.com/vol_4/chpt_3/10.html
Also notice that now Q4 can sink much smaller current from the load because know Ic4 = Iload + Ic3 before Q4 starts leaving the saturation region.
Got it..Thanks:smile:
 

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