Pinch-Off region of MOS-FET in punch-through?

[wolfgang6444]

TL;DR

I am trying to understand the pinch-off-region of an NMOS qualitatively as NPN-structure in punch-through

Summary: I am trying to understand the pinch-off-region of an NMOS qualitatively as NPN-structure in punch-through

I was always having trouble understanding what is going on in the pinch-off region of a MOS (say NMOS) Transistor.
Now I recently figured out, that this could be described (at least qualitatively) as NPN-structure in punch-through.
I would like some comments on this analogy:

One n-region would be the drain end of the channel, that is still inverted; thus effectively n-type.
The other n-region would be the drain contact.
The intermediate p-region would be the pinch-off-region, that is no inverted thus; p-type.

The drain to pinch-off region is a reverse-biased np-junction.
The corresponding space-charge region extends throughout the pinch-off region and generates an E-field at the channel to pinch-off "junction" - thus forward-biasing it (just like in punch-through). Thus the e- can enter from the channel into the pinch-off area where they are minorities and are swept out to the drain like all minorities being injected into a reverse biased junction.

Additional thought:
If a lateral spacing was deliberately introduced between gate-edge and drain-contact, no significant drain current would flow (neither for VDS<Vgeff nor VDS> Vgeff), except if the drain bias was that high, that this intermediate p-area would be in punch-through. This is kind of similar to the actual pinch-off area.

Is my analogy a vaild view on the subject?

Wolfgang

 

[trurle]

Summary: I am trying to understand the pinch-off-region of an NMOS qualitatively as NPN-structure in punch-through

Summary: I am trying to understand the pinch-off-region of an NMOS qualitatively as NPN-structure in punch-through

I was always having trouble understanding what is going on in the pinch-off region of a MOS (say NMOS) Transistor.
Now I recently figured out, that this could be described (at least qualitatively) as NPN-structure in punch-through.
I would like some comments on this analogy:

One n-region would be the drain end of the channel, that is still inverted; thus effectively n-type.
The other n-region would be the drain contact.
The intermediate p-region would be the pinch-off-region, that is no inverted thus; p-type.

The drain to pinch-off region is a reverse-biased np-junction.
The corresponding space-charge region extends throughout the pinch-off region and generates an E-field at the channel to pinch-off "junction" - thus forward-biasing it (just like in punch-through). Thus the e- can enter from the channel into the pinch-off area where they are minorities and are swept out to the drain like all minorities being injected into a reverse biased junction.

Additional thought:
If a lateral spacing was deliberately introduced between gate-edge and drain-contact, no significant drain current would flow (neither for VDS<Vgeff nor VDS> Vgeff), except if the drain bias was that high, that this intermediate p-area would be in punch-through. This is kind of similar to the actual pinch-off area.

Is my analogy a vaild view on the subject?

Wolfgang

Not valid. Punch-through do indeed happen in MOSFET transistors, and is manifesting itself as increase of leakage current at high drain voltage. Not related to normal conduction.
Also, at pinch-off current from channel to body (minority charges current in your terminology) plays no role in current limiting.

More useful description is to imagine pinch-off channel area as high value resistor of consistently n-type, with potential across that resistor gradually increasing from zero at source to Vg-Vth at pinch-off point. Because the voltage increase is created by flow of majority carriers current, the voltage in channel cannot increase beyond Vg-Vth, or gate to channel voltage would become too small to keep the n-channel open. The limitation of voltage drop across resistor is therefore limiting current through the resistor.