# Power System Fault Phasor Diagram

jaus tail

## Homework Equations

If load is inductive current lags voltage. If load is capacitive voltage lags current

## The Attempt at a Solution

Current lags voltage since wire is inductive.
So IF1 lags VF1 and IF2 lags VF2
But book says answer is C
Why should VF1 lag IF1? This will happen only if load is capacitor. But that is not mentioned in question.

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Do these faults take place at the same time so there's one solution,
or do they occur individually so there's two separate solutions ?

What direction of current is assumed positive ?

old jim

jaus tail
They haven't mentioned anything. Only this question. I found two solutions from internet. One says:
When fault takes place at F1, current is feeding into the BUS A. It is like a generator delivering power to bus A----> So Vf1 lags If1
When fault takes place at F2, F2 point is like a load taking power from generator----> So Vf2 leads If2
So they've said C is the right answer.

Other website said that fault always takes reactive power so Vf1 will lead If1 and Vf2 will lead If2
I also think this should be the right answer but many internet sites said the earlier one is the right answer i.e option C. I didn't understand that underlined part above.

jaus tail
I guess the faults take place independently. That is why they say 'if the fault takes place at location F1' in the question.

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What direction of current is assumed positive ?

make that what direction is shown positive ? Look at your diagram.

jaus tail
I guess positive current is from left to right. Since voltage at A is leading voltage at B, so active power will flow from A to B (Don't know about reactive power) (assuming Ea = Eb).

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You're almost there. Draw phasor diagram ?

jaus tail
I did that. Still not getting answer C.

In both cases the fault current lags the voltage at bus A.

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Haste makes waste. I think your diagram is less than rigorous in assigning current directions.

But current is defined in problem statement as what flows at bus A which is in between the two fault locations.

Will current there not flow toward the fault ?
If so,
In one case does it flow through A left to right , same way arrow is pointing, and in other case through A right to left, opposite the arrow ?
What would that do to its phasor?

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jaus tail
jaus tail
Wow... This was so difficult. How do I go through all this in the exam. I couldn't have thought of this during the exam.

Is my above phasor right? What would the Ea be? Is that Va or Vf1?

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What would the Ea be?
What is voltage at location of the fault ? Does EA matter at all ?

Is my above phasor right?
With no labels i don't know what it is that you drew.

Aha there's your next thought step.
What is the current flowing through A to reach the fault ?
Negating AC current shifts its phase 180 degrees, doesn't it ?

Think in simple steps. Write them out one per line.
That's probably the point of this homework problem.

Good luck in your studies. Remember, success is 1% inspiration 99% perspiration . So orderly disciplined thinking is your best ally.

old jim

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jaus tail
jaus tail
Thanks. Is this the right phasor?

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Thanks. Is this the right phasor?

Red line represents what ? I thought the fault was at F1 not at bus A.

I(FA) looks like a reasonable guess since we don't know the angle δ .so can't draw a phasor for VA.

If V(f1) is zero why does your Black V(f1) phasor have nonzero length ? Are you saying it's the voltage at the fault, its lowercase "f" distinguishing it from voltage at bus A which has uppercase" F" VF1 ?

Were your fault at bus A then the voltage there would be zero. But there's some fraction of line impedance between Bus A and fault F1 .

Current through A is pushed toward the fault F1 by EB. Voltage at bus A, confusingly named VF1 instead of VBusA, is therefore nonzero.
It'll be some fraction of EB by voltage divider action. So we could draw a phasor for it . We could call it either VBusA, or VF1 .. It'll have same phase as EB just shorter length.

Were your black phasor labelled EB and VF1's phasor just a portion of EB 's i'd like your diagram a lot better.

Brown IF1 looks okay, i think you see that it has to be drawn up not down because of the current directions assigned.

That rigorous attention to detail is what it takes to get through EE. You'd best develop the self discipline now.
It's easy to do. What is difficult is to overcome our desire to leap straight to an answer instead of walking there one little step at a time..
That's mental laziness - recognize it as forbidden fruit .

This problem really boils down to basic circuit analysis. Be attentive to labels and assigned polarities and the algebra will work out.

old jim

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jaus tail
jaus tail
Yeah i drew fault at wrong place. Red line should be at a bit left.

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I understand the pressure of university level coursework. They feed it to you fast.

It seems counterintuitive at first to work slow and methodical . Simple problems can often be done by inspection.
As the coursework subjects grow more complex 'slow and methodical' becomes a must.
Remember the fable of "Tortoise and Hare"..

old jim

jaus tail
jaus tail
Thanks.

jim hardy