Propagation Delay of Traces on PCBs

  1. I am concerned about getting the same length to all RAM chips (the output is equidistant to all inputs of the different chips)

    I heard somewhere that a rule of thumb is that you get .18 nanoseconds of time delay for every inch of tracing. Is this accurate? Is it safe to use this when making decisions on differences in trace lengths? For example, the RAM is clocked at 100 MHz, and one RAM has an extra .88 inches of tracing for some of its data lines than its others. Using the rule of thumb, that would be about .16 nanoseconds delay to the longer traced data lines, and .16 nanoseconds is probably negligible relative to the 10 nanosecond clock cycle of the RAM (i know I would need to take into consideration the time delay on the clock trace as well).

    Does this sound reasonable?

    Also, where would someone get a number like .18 ns /inch? I did the conversion and this is considerably slower than the speed of light, a little less than half the speed at 1.41 million meters /sec. How would a trace slow the signal by this much?
  2. jcsd
  3. berkeman

    Staff: Mentor

    Here is a basic article about transmission lines:

    and the link to "stripline" transmission lines part-way down the page will help you see how the PCB trace (over an adjacent ground plane layer -- very important!) forms a transmission line.

    The propagation velocity is related to the inductance per unit length and the capacitance per unit length (which are the main components of the characteristic impedance Zo of the transmission line). A ballpark figure for a PCB trace is about c/1.5, but it varies a fair amount, based on the dielectric constant of the PCB material forming the stripline.

    There are *lots* of things you need to get right if you are laying out a PCB with high-speed RAM on it. I highly recommend that you buy or check out a copy of the book, "High-Speed Digital Design, A Handbook of Black Magic", by Howie Johnson and Martin Graham. Pay special attention to Chapter 4 on Transmission Lines, and Chapter 11 on Clock Distribution.
  4. thank you very much, I had a course with transmission lines, but it was very abstract and I have never applied it to a PCB. I know that Zo of the PCB is determined by PCB manufacturer parameters, and I can match this impedance on the microprocessor end (it has registers that allow you to change its drive strength), but there are none for the SDRAM end. I have no termination resistors, because I was hoping that the drive strength adjustments could compensate. I am very concerned with noise and emissions, but also that my signal timing is correct as far as the timing diagrams between my two chips. I know it is not an art, but it is very hard to negotiate between PCB layout ease and ideal traces. I am sort of blind, but I know some basics like thick power traces, perpendicular routing on different planes, short trace lengths etc.

    Is that book very expensive and how technical is it?
  5. so the number i was given .18ns/inch works out to be about c/2.13, and your number is c/1.5 (.13ns/inch, which is more forgiving. So even with a trace length of almost 8 inches, I only will get a delay of 1 ns. Since this is in a small area, wouldn't trace length be almost negligible at 100MHz? I'm not trying to argue, but I hope you could tell me why this is not negligible with respect to timing.
  6. berkeman

    Staff: Mentor

    The book is about $100 new, and about $40-50 used on

    Your local technical library should have copies that you can check out to see if you like it and how useful you think it is. There are plenty of other sources of information on the subject too, and a google search for high speed pcb layout tutorial (or similar keyword phrase) should get you some intro material.

    BTW, your source termination idea is good, and that is a fine way to terminate digital point-to-point transmission lines. You do get a positive reflection off the receiving device, but that reflection is terminated in the Zo of the source gate, and does not cause ringing at the receiving gate. "Source" or "Back" termination like that works well for point-to-point (not multi-drop) transmission lines, and consumes way less power than a traditional Zo forward termination at the end of the TL. (Quiz question, why?)

    One point to keep in mind (there are many others) -- do NOT feed your TL trace through the PCB. It needs to start and end on the top outer layer of the PCB, and the ground plane of the next inner layer down the stackup needs to be clean and not all cut up with vias or traces near the TL trace. If you feed the TL trace through a via to the opposite side of the PCB, you will have a bad positive pertubation in the Zo that the signal on that trace sees. Microstrip TLs do not include vias, so you need to keep that in mind in your floorplan for the uP and RAM. Start your PCB floorplan with the uP and RAM, get them right so that you can route the TLs on the top side of the PCB undisturbed, and then grow your floorplan out from that core.
  7. berkeman

    Staff: Mentor

    Holy crap! I hope you're kidding about the 8 inch number. You need the RAM right next to your uP, not 8" away.

    The propagation delay number depends on the microstrip TL numbers. Just see the references for better numbers. The differential prop delay numbers that you get will to into your timing inequality checks, to be sure that you are meeting the timing numbers with margin.
  8. Nooo, I'm just saying that even if I did have a trace that long, from the c/1.5, I would only get a 1 ns delay, I'm not that naive to actually make a trace that long :P

    I want all of my traces to be the same length from one stage to the next, such that I dont want my MSB of data getting to my RAM chip 1 ns after my LSB and clock did for the possibility of clocking in wrong data. If my layout dude has to give my MSB an extra .88 inches of trace, then the timing offset will only be a fraction of a ns, so I am hoping that will be ok.

    It just is really hard for me to push for all trace lengths to be the same since this makes it difficult on layout and the technician who is doing my layout has been doing layouts longer than I've been alive even, so its hard for me to push him to do it my way when he doesn't like it.

    I am basically trying to make the layout as simple and straightforward as I can since I don't know t-lines the best. I want all signals to reach each chip at the same time, and someways we're having to put half of a bus to the first chip down and then down to a second and the other half to the second chip first and then up to the first chip, which gives signals a differential in timing. It makes me nervous, but I'm hoping it works =/
  9. berkeman

    Staff: Mentor

    Okay, whew. Had me worried there for a moment. The traces do not need to be exactly equal in length, not at the speeds you are talking about. But any differences do need to be factored into your memory interface timing calculations (the timing inequalities I mentioned earlier).

    Here is a reference to an old paper I helped write many years ago for a slower memory interface (10MHz). It lists some of the timing inequalities that you should be thinking about and explicitly checking:
  10. Also, does that book go much into EMI and EMC? I could use both that and PCB layout together since I know they're are important to eachother.
  11. berkeman

    Staff: Mentor

    Yes, it does address EMI from several different angles. Can you say what kind of device you are designing? How big is it, and what kind of cables go in and out of it? Are there previous versions of this device that you can use to help you understand the EMI considerations?
  12. I can't say a lot because it is confidential, but it is an embedded system with a uP that runs a cumbersome operating system, it has a lot of peripherals, and it has a harness with unshielded cable that comes out of it (the antenna for all our EMI). It is an industrial/automotive app and we have to be very meticulous in our design for EMI/EMC and ESD. There are a few previous versions, and I am always trying to pick up as much as I can from them and their designer, who could be considered a practical EMC expert as much as anyone I've met. I am doing the digital side of things and system architecture mostly, which no one on this project has ever done (it was outsourced before), and I am straight out of school so this is my first real project ever. I'd say there are a lot of EMI design methods that were done, but also they had gotten lucky on some issues before, and there are maybe even some more issues that might not be known that could explain some of the failures that have happened in the field for the previous products. I don't want to say anything specific since I need to keep my job :P

    I think I am going to buy that book and use it to do an analysis on my design, since I know it will impress people and will be very important for troubleshooting later on, which I am nervous about.

    Edit: I should also say that the memory bus has A LOT of stuff on it, and that is why it has become such an issue for layout.
    Last edited: Dec 28, 2007
  13. berkeman

    Staff: Mentor

    Another EMC book that you might look into is the classic "Noise Reduction Techniques in Electronic Systems" by Henry Ott:

    It's an older book from the early days of EMC in the US (1980s/90s, when the FCC started imposing mandatory limits on unintentional EMI), but still has a lot of good info. The experienced engineer that you mentioned where you work may have a copy you can borrow as well.
  14. I think there is some confusion. While talking about digital signals, you need to consider the rise time of control signals/data signals (whichever is faster) for wavelength calculation. What you need to make sure is your reflections should be settled within the rise time.
  15. 100MHz can work after 8" of length (need to make sure timings are affordable, like the delay for data after giving #RD signal). As long as you keep traces in same layer with affordable trace impedance and a series termination near to strong driver, it will work.
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