Dismiss Notice
Join Physics Forums Today!
The friendliest, high quality science and math community on the planet! Everyone who loves science is here!

Circuit designs with crystals and layout of digital clock lines

  1. May 20, 2008 #1
    I have two different types of questions regarding crystals and clocks. I can't remember if I've asked these question before. I'd appreciate any input on this topic.

    Crystal external circuitry:

    Almost any IC with an external crystal has two pins to connect to it. Now my question is how do the designers determine if they should use shunt capacitors from the crystal traces to ground, and also how do they determine what values to use? I see typically 18pF to 47pF. Also how do they determine if they should use a load resistor parallel to the crystal and how do they determine what value to use? I have seen values between 1M Ohm and 5M Ohm. Are they figuring some kind of RC constant with this? I have gotten lucky and seen reference designs or some data sheets specifying what to do (not all do though), but how do they come up with these values???

    Digital Clock signals:

    My high speed digital design book says to provide extra gap spacing between adjacent traces to my clock signals. They also say to keep as close to ground as possible. This helps kill cross talk. Is it too much to try to carve your clock trace through an internal ground plane, or does that screw with the impedance too much and create loop currents by disrupting the ground plane? Also, is it better to use load resistors at the receiving circuits to terminate clock signals in order to match trace impedance, or is it better to use a series termination resistor at the clock source IC pin, or both? Finally, I've looked at very high speed clock traces on some example boards, and the traces seem to actually be layed out physically in a square-wave geometry (it zigzags on the board). What is the purpose of this and the reasoning behind it? My guess would be it is done just to give it length for propagation delay, but I'm curious if there is a more physics/transmission line type explanation.
  2. jcsd
  3. May 20, 2008 #2


    User Avatar

    Staff: Mentor

    The crystal has been tuned to be on-frequency for some load capacitance (for a parallel resonant oscillator architecture, which is the most common for uCs). So your circuit should use parallel capacitors that match the total parallel load capacitance that the crystal is tuned at the factory for. If you specify an 18pF parallel resonant crystal, then the sum of the two parallel capacitors on your PCB plus the sum of the input capacitances of the two uC pins, should add up to the parallel capacitance value of the crystal spec.

    The external resistor values (if any) come from optimizing the performance of the oscillator circuit in the uC. If there is a series resistor specified (typically in the 200-300 Ohm range), that is to help prevent early aging of the crystal due to overcurrent drive by the oscillator. If there is a parallel resistor specified (typically in the 100k to several MegOhm range), that is to help keep the oscillator inverter gate in the linear region. If the uC is meant to work mainly with one frequency crystal, these external resistors and caps are generally pulled inside the chip, to save overall cost. If the uC is meant to allow different values of crystal frequencies, then these parts will generally be external, with different values based on the frequency.

    To use a forward termination (Zo at the destination), you need a lot of power by the drive gate. Just do the math to figure out how much current it takes to drive Vih and Vil into a full split forward termination of 75 Ohms or so, and compare that to typical digital logic gate Iout capability. Lot of power. So, it is more typical to back terminate (with R = Zo - Rout of the drive gate) right at the drive gate's output pin. The serpentine pattern you observe is generally used to keep the clock trace on one outer layer of the PCB, on the side just above the ground plane (not the power plane). You do not want to use vias on a clock trace, because that disrupts the clean Zo that you want to present for the clock transmission line. That's the reason you wouldn't want to bury the clock line -- that would require a via to bury it, and more vias to tap into it. It would also cut the ground layer as you say, which would be a bad thing (for this application).
  4. May 21, 2008 #3
    For run of the mill crystals, I've never had much problem just using the suggested values for capacitors in the databook.

    For watch crystals at 32,768Hz, it's a whole different game...

    I spent about an hour or so getting a PIC to run with a 32kHz xtal (it required 68pF caps), and even longer getting a 4060 to oscillate reliably with one...

    For the 4060 it was a case of adjusting capacitor values and the series & shunt resistor values until the thing started reliably and didn't stop oscillating after a while. All very empirical.
Know someone interested in this topic? Share this thread via Reddit, Google+, Twitter, or Facebook

Have something to add?

Similar Discussions: Circuit designs with crystals and layout of digital clock lines
  1. Digital Clock Project (Replies: 13)

  2. Circuit layout (Replies: 22)