I have two different types of questions regarding crystals and clocks. I can't remember if I've asked these question before. I'd appreciate any input on this topic. Crystal external circuitry: Almost any IC with an external crystal has two pins to connect to it. Now my question is how do the designers determine if they should use shunt capacitors from the crystal traces to ground, and also how do they determine what values to use? I see typically 18pF to 47pF. Also how do they determine if they should use a load resistor parallel to the crystal and how do they determine what value to use? I have seen values between 1M Ohm and 5M Ohm. Are they figuring some kind of RC constant with this? I have gotten lucky and seen reference designs or some data sheets specifying what to do (not all do though), but how do they come up with these values??? Digital Clock signals: My high speed digital design book says to provide extra gap spacing between adjacent traces to my clock signals. They also say to keep as close to ground as possible. This helps kill cross talk. Is it too much to try to carve your clock trace through an internal ground plane, or does that screw with the impedance too much and create loop currents by disrupting the ground plane? Also, is it better to use load resistors at the receiving circuits to terminate clock signals in order to match trace impedance, or is it better to use a series termination resistor at the clock source IC pin, or both? Finally, I've looked at very high speed clock traces on some example boards, and the traces seem to actually be layed out physically in a square-wave geometry (it zigzags on the board). What is the purpose of this and the reasoning behind it? My guess would be it is done just to give it length for propagation delay, but I'm curious if there is a more physics/transmission line type explanation.