Redraw Equivalent Circuit for 3-input OR gate

Click For Summary

Discussion Overview

The discussion revolves around how to redraw a three-input OR gate circuit using only 2-input NAND gates. Participants explore the application of De Morgan's laws and the requirements for the circuit design, including specific output conditions.

Discussion Character

  • Technical explanation
  • Debate/contested
  • Homework-related

Main Points Raised

  • Some participants suggest using De Morgan's laws to create a 2-input OR gate from NAND gates, proposing that a NOT gate can be formed by connecting the inputs of a NAND gate together.
  • One participant presents the equation from De Morgan's law, indicating a method to express the OR operation in terms of NAND operations.
  • Another participant expresses difficulty in combining all possible input combinations to achieve the desired circuit, indicating a lack of clarity in the problem requirements.
  • There is a claim that the original question specifies the output of the OR gate should be high when at least two out of three inputs are low, which is contested by another participant.
  • Some participants propose combining outputs from AND gates formed by pairs of inputs (A AND B, B AND C, A AND C) as part of the solution.
  • A later reply questions whether the goal is to implement a majority circuit, suggesting that the complexity of the solution may be equivalent to implementing the entire problem with NAND gates.
  • One participant requests clearer problem statements in future posts, indicating a need for better communication in the discussion.

Areas of Agreement / Disagreement

Participants do not reach consensus on the specific requirements of the circuit or the interpretation of the problem statement. Multiple competing views exist regarding the output conditions and the approach to solving the problem.

Contextual Notes

There are unresolved assumptions regarding the problem requirements, particularly the output conditions for the OR gate. The discussion also reflects varying levels of clarity in the initial problem statement.

Deathfish
Messages
80
Reaction score
0
How do you redraw a three-input OR gate circuit using only 2-input NAND gates?
 
Physics news on Phys.org
Using De Morgan's laws, you should be able to figure out how to make a 2-input OR gate using NAND gates. You can make a NOT gate by wiring the NAND inputs together.
 
DeMorgan's law says
\overline{A+B}= \overline A\cdot \overline B

or

A+B = \overline{\overline A\cdot \overline B}= NAND(\overline A,\overline B)

So start with A + (B + C)...
 
Deathfish said:
How do you redraw a three-input OR gate circuit using only 2-input NAND gates?

You know the rules, Deathfish. Show us your work!
 
i've worked on this, but i seem to be going back and forth combining all combinations ie. 3C2 with no luck... difficult to explain this here. I know the equivalent of 2-input OR gates... but i am required to draw up 3-input OR gate when i am given just 2-input NAND gates. The question is to output HIGH when at least 2 out of 3 inputs are LOW.
 
Deathfish said:
i've worked on this, but i seem to be going back and forth combining all combinations ie. 3C2 with no luck... difficult to explain this here. I know the equivalent of 2-input OR gates... but i am required to draw up 3-input OR gate when i am given just 2-input NAND gates. The question is to output HIGH when at least 2 out of 3 inputs are LOW.

A 3-input OR gate does not "output high when at least 2 out of 3 inputs are low"...
 
its part of the question... A AND B, B AND C, A AND C then combine them together..
 
Deathfish said:
its part of the question... A AND B, B AND C, A AND C then combine them together..

Part of what question? Your original post says nothing about AND gates.
 
figured the first part out just need to combine that using three-input OR gate..
 
  • #10
Just guessing, are you trying to implement a majority circuit where two or more of A,B, and C are true? If so, it probably will take as many NAND gates to implement the 3 input OR gate by itself as it would to do the whole problem with NANDs in the first place.
 
  • #11
Deathfish said:
figured the first part out just need to combine that using three-input OR gate..

Thanks for being so clear in your OP. In the future, use the Homework Help Template, which asks for the exact problem statement.

I'm out.
 

Similar threads

Engineering Combinational Logic Circuits using Logic Gates
  • · Replies 1 ·
Replies
1
Views
2K
Engineering Drawing the Schematic for a Circuit I built on a Breadboard
  • · Replies 11 ·
Replies
11
Views
2K
Comp Sci Digital Logic 8 Bit Full Adder Circuit
  • · Replies 5 ·
Replies
5
Views
3K
Engineering Draw the equivalent circuit using only NAND gates
  • · Replies 8 ·
Replies
8
Views
3K
Engineering Output waveform after input rising edge and before output falling edge
  • · Replies 14 ·
Replies
14
Views
3K
Engineering Longest Path in a Combinational Circuit
  • · Replies 14 ·
Replies
14
Views
5K
Engineering Drawing Circuits: Correctly Drawing NAND and NOR Gates with 2 Inputs
  • · Replies 1 ·
Replies
1
Views
2K
Engineering What is the significance of a -4V gate potential in FET-transistors?
  • · Replies 9 ·
Replies
9
Views
2K
ASIC Logic Gates NAND Homework: Solving 2-Input NAND Gate Circuit
  • · Replies 9 ·
Replies
9
Views
3K
Engineering Calculation of the Transconductance for a MOSFET
  • · Replies 5 ·
Replies
5
Views
7K