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Engineering Output waveform after input rising edge and before output falling edge

  • Thread starter jaus tail
  • Start date
588
43
Homework Statement
Draw any circuit (combinational, sequential to get this waveform)
Homework Equations
And gate with one input using buffer of another input for some delay
1565977075163.png


A is given waveform, we have to use circuits to get B and C waveform. For B we can use an And Gate with 2 inputs, X and Y. X is buffered (to get some delay) and is fed to Y input of And Gate. So we'll get waveform B.

But I don't know how to get C waveform. The question is that even if I extend A, then the falling edge of C must always occur one clock cycle before input A. Is this circuit even possible? I don't think so.
 

berkeman

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Do the vertical lines represent clock edges that are available to you to build this circuit? Or do you need to do this all with RC delays?
 

NascentOxygen

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For B we can use an And Gate with 2 inputs, X and Y. X is buffered (to get some delay) and is fed to Y input of And Gate. So we'll get waveform B.
It does appear that B is to be held low for precisely one clock cycle delay. Is this image an accurate representation of the specification? If true, then the switching delay of a gate is unlikely to be a satisfactory answer.
 
588
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Vertical lines represent clock edges. The professor said you can use whatever circuit you feel like. The professor was convinced when I said use buffer gates and And gate for B waveform, but then he asked can C ever be done.
 

berkeman

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NascentOxygen

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but then he asked can C ever be done.
If these are to be kept real time, then with A being of unforeseeable length, it is not possible to set C to low at a time one clock cycle ahead of A going to low.
 

Tom.G

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If these are to be kept real time, then with A being of unforeseeable length, it is not possible to set C to low at a time one clock cycle ahead of A going to low.
Agreed. The only way it makes sense is if C is interpreted as a duration. This is based on the statement by the OP that
Vertical lines represent clock edges.
 
588
43
Yeah even I was like mostly sure that it can't be done. We can't anticipate the falling edge of the input without any previous information.

Maybe it can be done if like we have history. Like one clock cycle of input passes and from second clock cycle, we want the output to act in a particular way as compared to the input. Like input is a sqaure wave and output is a wave with rising edge after rising edge of input and output has falling edge before falling edge of input. Maybe it can be done from 2nd clock cycle.

The first one can be done like this:
1566458066996.png


And gate is there and there are 2 inverters. So the rising edge of 'And' output will be after some time the input rises from 0-1.
 

Tom.G

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Maybe it can be done from 2nd clock cycle.
I think you are on the right track there.

I do have a question about the leading edges of B and of C though. Can they occur after any delay, or must they occur at a Clock pulse?

Cheers,
Tom
 
588
43
I wasn't told about anything about that. Just a few waveforms were drawn by hand and then I was asked if I can get them as output. I suggested using And gate and buffers for the first waveform where only the leading edge has a delay. For the second waveform, i tried but eventually said it couldn't be done.
 

berkeman

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Sorry, I'm not seeing the difficulty. It seems like you can just use various types of FFs and some logic gates to make the two bottom waveforms from the top waveform and the clocks supplied...
 
588
43
Sorry, I'm not seeing the difficulty. It seems like you can just use various types of FFs and some logic gates to make the two bottom waveforms from the top waveform and the clocks supplied...
How can you make the bottom waveform? How can we get the falling edge of the output, before the falling edge of the input?
 

berkeman

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You said the vertical lines are clock edges. Just count clock edges...
 

NascentOxygen

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How can you make the bottom waveform? How can we get the falling edge of the output, before the falling edge of the input?
Delay everything by one clock cycle. This provides you with a one-clock-cycle lookahead in time. Waveform A as displayed on the oscilloscope thus becomes a delayed version of the realtime waveform A.
 
588
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True that they are clock edges but I don't know time period of A. if A is high for 4 clock periods, then C must be high for 2 clock periods (rise one clock period after A, and fall one clock period before A). And if A is high for 7 clock periods then C is high for 5.
The delaying A makes sense. I create circuit such that output rises after 2 clock periods of A, and output falls same as when A falls, only after this circuit, I further delay A by 1 clock period and this becomes A'
So output rises one clock period after A' and output falls same as when A falls, thus it falls 1 period before A'
 

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