Synchronous Buck Converter Vds and Ids Waveforms Analysis

[Ms FYP]

Hi,

I'm simulating the Synchronous Buck Converter as per attached, to obtain the Vds and Ids for the High Side switch and I'm using P-mosfet as the switch and Microsim PSPICE software to simulate the circuit. once it is done, i obtained the Vds and Ids waveforms as per attached.

my question is, why the Vds and Ids for the high side switch are not overlap to each other?
Is there something wrong with the circuit that i have designed?

really appreciate that if anyone could share some ideas regarding this problem..

many thanks..

 

[berkeman]

Hi,

I'm simulating the Synchronous Buck Converter as per attached, to obtain the Vds and Ids for the High Side switch and I'm using P-mosfet as the switch and Microsim PSPICE software to simulate the circuit. once it is done, i obtained the Vds and Ids waveforms as per attached.

my question is, why the Vds and Ids for the high side switch are not overlap to each other?
Is there something wrong with the circuit that i have designed?

really appreciate that if anyone could share some ideas regarding this problem..

many thanks..

Why is PWM1 returning to the inductor instead of ground?

The value of the inductor looks pretty low, but you appear to be running the frequency pretty high, so maybe it's okay.

The bottom transistor will see the flyback voltage go below ground -- are you driving its gate correctly to accommodate that?

Could you show a plot of PWM1, PWM2 and the input voltage to the inductor?

 

[Ms FYP]

hi berkeman,

thanks for replying my post..

Oh sorry..i miss that one..it should be connected to ground..
Here is the PWM1, PWM2 and input voltage to the inductor.
and yes..i'm driving this circuit at high switching frequency, that's why the value of the inductor is small.

i have attached two plots for both of them.. one is when the PWM1 is returning to inductor instead of ground and another one is when it is connected to ground...it seem that they have kinda same waveforms...

thanks~

 

[berkeman]

hi berkeman,

thanks for replying my post..

Oh sorry..i miss that one..it should be connected to ground..
Here is the PWM1, PWM2 and input voltage to the inductor.
and yes..i'm driving this circuit at high switching frequency, that's why the value of the inductor is small.

i have attached two plots for both of them.. one is when the PWM1 is returning to inductor instead of ground and another one is when it is connected to ground...it seem that they have kinda same waveforms...

thanks~

Weird. Could you please add the current through the inductor to the first plot (the one with the gate drive with respect to ground for both devices)?

 

[vk6kro]

The PMOS FET is shown upside down in that circuit.

Also, the L and C form a series tuned circuit at about 52 KHz without the 3.5 ohm resistor and, with the resistor, they produce a low pass filter that doesn't pass anything much above 80 KHz.You could consider exchanging the two FET positions, but it would be better to find a working circuit and just copy it.

 

[Ms FYP]

The PMOS FET is shown upside down in that circuit and it needs the gate to go more positive than the source if it was connected that way.

Also, the L and C form a series tuned circuit at about 52 KHz without the 3.5 ohm resistor and, with the resistor, they produce a low pass filter that doesn't pass anything much above 80 KHz.
As your signal is at about 1 MHz, this will cause a problem.

You could consider exchanging the two FET positions, but it would be better to find a working circuit and just copy it.

Hi vk6kro,

thanks for your replied..
i will try to exchange the position for both of the FETs and see the results..

many thanks~

 

[berkeman]

Hi vk6kro,

thanks for your replied..
i will try to exchange the position for both of the FETs and see the results..

many thanks~

No, your highside FET looks okay. It's your lowside FET that looks upside-down. Quiz Question -- Why?

 

[vk6kro]

A P-Channel MOSFET should have its drain more negative than the source.

In this case, it is more positive.

So, why do you feel it is OK?

[PLAIN]http://cnx.org/content/m1029/latest/4.48.png

 

[Ms FYP]

Weird. Could you please add the current through the inductor to the first plot (the one with the gate drive with respect to ground for both devices)?

hi berkeman,

sorry..just came back from class..here is the current through the inductor for the inductor for the gate drive with respect to ground.

 

[vk6kro]

Most of that current is DC. The actual change in current is (950 mA - 825 mA) or 125 mA.

Did you measure the voltage across the 3.5 ohm resistor?

 

[Ms FYP]

Most of that current is DC. The actual change in current is (950 mA - 825 mA) or 125 mA.

Did you measure the voltage across the 3.5 ohm resistor?

hi vk6kro,

yes, i have measured the voltage across 3.5 ohm resistor and attached is the waveforms.
hmm..may i know, is the duty ratio actually effected the switching of the PMOS FET? i mean.. can it become the reason why the Vds and Ids are resulted as shown in previous attachment? this is because, this circuit is driven with duty cycle of 0.25 and 1MHz switching frequency. so the expected output voltage should be 3v.

thanks..

 

[gnurf]

If the PMOS is connected as shown, won't the device's body diode conduct when the switch is supposed to be off?

Re: the low-side switch quiz question, the source is grounded so as long as the driver can overcome the threshold voltage of the device, the current configuration should be fine, no? Also re the suggested swapping of the FETs, I can't see any good reason to use a PMOS as the synchronous rectifier?

Maybe the OP could post his updated schematic/waveforms with 1) the high-side PMOS connected with its source towards Vi and drain towards vnode, and 2) PWM1 properly grounded.

 

[Ms FYP]

Maybe the OP could post his updated schematic/waveforms with 1) the high-side PMOS connected with its source towards Vi and drain towards vnode, and 2) PWM1 properly grounded.

hi gnurf,

many thanks for your replied..
here i updated the schematic and waveforms for the circuit. and yet..i still obtained the same vds and ids results..

 

[gnurf]

Maybe the OP could post his updated schematic/waveforms with 1) the high-side PMOS connected with its source towards Vi and drain towards vnode, and 2) PWM1 properly grounded.

Please try again.

 

[gnurf]

By the way, it seems to me that you're pushing the cart before the horse a little bit here. Why not try the simplest solution first? That is, replace the synchronous rectifier (M2) with a free-wheeling diode so that you have a conventional buck converter.

When you're familiar with that and it's waveforms (e.g., why is the diode needed, why does the inductor current ramp up and down, how is the dutycycle related to the output voltage, etc), you can add another piece to the puzzle: the synchronous rectifier. Just leave the diode as it is (it'll provide a conduction path during the deadtime) and place M2 in parallel. Now you can compare the switch-node ("vnode") waveform with the one you got with only a diode and hopefully be understand better how the synchronous buck converter improves efficiency compared to its conventional counterpart.