Should Unused Inputs in a Quad 2 Input NOR Gate IC be Tied to Ground or Vcc?

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Discussion Overview

The discussion revolves around the proper handling of unused inputs in a quad 2 input NOR gate integrated circuit (IC). Participants explore whether these unused inputs should be tied to ground or Vcc, considering implications for current draw and output behavior.

Discussion Character

  • Technical explanation
  • Debate/contested

Main Points Raised

  • Some participants suggest that unused inputs should be tied to ground to prevent them from floating, which could lead to excessive current draw and output oscillation.
  • Others argue that tying unused inputs to ground would result in a high output, potentially drawing excessive current, and propose tying them to Vcc instead to keep the output low.
  • A participant notes that the current draw of a properly operating logic gate IC is influenced by what is connected to the output, indicating that leaving the output unconnected may minimize current draw.

Areas of Agreement / Disagreement

Participants express differing views on whether unused inputs should be tied to ground or Vcc, indicating that the discussion remains unresolved with multiple competing perspectives.

Contextual Notes

There are assumptions regarding the behavior of CMOS inputs and outputs that are not fully explored, including the specific conditions under which current draw may vary.

TheRedDevil18
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I have a quad 2 input NOR gate ic in which I am only using two of the four gates. I have read on the internet that unused inputs must be tied to ground. But if I tie these inputs to ground then I would get a one on the output. Will that draw excessive current ?, should I tie them to Vcc instead so my output is zero ?
 
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TheRedDevil18 said:
I have a quad 2 input NOR gate ic in which I am only using two of the four gates. I have read on the internet that unused inputs must be tied to ground. But if I tie these inputs to ground then I would get a one on the output. Will that draw excessive current ?, should I tie them to Vcc instead so my output is zero ?
You can tie them either way -- the key is not to let any CMOS inputs float, since they can float to mid-rail, which draws excessive current in the input stage, and can make the output oscillate creating noise. Whether the (open) output pin is high or low doesn't affect the Idd current draw for the CMOS gate.
 
To build on what Berkeman said a properly operating logic gate IC will draw current based on what is hooked to the output. So if you hook nothing to the output, you will draw the least current that is possible.
 
Thanks guys
 

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