# Homework Help: Signal to Noise ratio calculation

1. Apr 20, 2013

### DesirePRG

A 200mv peak to peak sinusoidal signal is applied to an ideal 12 bit A/D converter, for which Vref(v p-p full scale) is 5v. Find signal to noise ratio.

This is a problem worked out by one of my lecturer and the answer seems to be 46dB. But I am confused on his method. Is there anyone who could explain me how the result was worked out?

2. Apr 20, 2013

### the_emi_guy

46dB is indeed the correct answer. There are about a half-dozen steps involved. Perhaps we should start with which steps you understand and which you are having trouble with?

3. Apr 21, 2013

### sophiecentaur

How can a figure for SNR not strictly relate to bandwidth and, in the case of an ADC, the sampling rate?

4. Apr 21, 2013

### the_emi_guy

Bandwidth comes into play when we are dealing with thermal noise. On a 12bit ADC the quantization noise caused by the discrete steps is much larger than thermal noise floor (generally). In this case the step size is 5V/2^12 = 1.22mV and the corresponding rms quantization noise is step size divided by square root of 12 netting 0.35mVrms.

His signal is 70.7mVrms, thus SNR of 46dB.

There are some assumptions made, particularly that the sampling rate is uncorrelated to the sampled signal. In the case if a sinewave this may not be true depending on its frequency, but this is the standard textbook computation.

5. Apr 21, 2013

### carlgrace

That's not true generally. I design ADCs for communications and imaging applications. For communications almost always a 12-bit ADC will have 10-bit noise performance and 12-bit linearity. For imaging applications it can sometimes be close to 12-bit noise. The power of a Nyquist-rate ADC grows 4X when you add one more bit of SNR (all other things being equal) so typically commercial ADCs do not have true 12-bit noise performance.

It works out that way in this example because the input signal is using only a small part of the ADC's dynamic range.

6. Apr 22, 2013

### sophiecentaur

Bandwidth is there, whatever the added impairements may be. Once the distortions caused by the quantisation are 'random' enough to be noiselike then you treat them like thermal noise. In a good enough quality ADC (sufficient sample levels), the level of quantising noise can be as low as you want.

Are you aware of the technique of over-sampling? (See this wiki link)It can work well even for a one bit ADC. The reason that it works is that the energy in the steps between samples is, in fact, spread over a bandwidth equal to the sample rate. (or is it half?- I can't remember, but no matter). The noise energy falling in the bandwidth of the baseband signal will drop by 3dB, every time the sampling frequency is doubled. Audio sampling at many MHz has been used very successfully to produce marked improvements in quantising noise for low bit number ADCs. The advantage is that an ADC with few steps can be made more linear and, as long as it can be made to operate fast enough, the net result is better.

7. Apr 22, 2013

### the_emi_guy

Hey, good topic folks! Maybe we should move this back to EE forum, this is something I have pondered.

Generally when I see noise levels in the millivolts or hundreds of microvolts caused by thermal noise I am dealing with both wide bandwidth and high gain. The unity gain ADC front end amp couldn't possibly have poor enough thermal noise figure to add hundreds of microvolts of noise could it?

Consider the AD10200 (Analog Devices, 12-bit, first one on their list). This is a 250MHz bandwidth part with 50 ohm input.

Theoretical SNR due to quantization (SQNR) in dB below full scale
for 12-bits is 74dBFS or 0.14mVrms of noise

Advertized SNR = 67dBFS = 0.32mVrms.

Thus there is 0.18mVrms of noise in excess of quantization noise, or -62dBm.

If we assume that this is thermal noise, and that the device has 250MHz bandwidth, than this is
-86dBm/1Hz. This is 88dB above the thermal noise floor of -174dBm/Hz.

In other words this part's analog front end would have to have a noise figure of 88dB against thermal noise even though it has no gain! Even a crappy unity gain voltage feedback OP amp with large resistor values would have noise figure below 50dB.

I suspect that the excess noise in the SNR spec is due to other impairments such as clock jitter.

We generally use sigma delta modulation in cases where have excess bandwidth and can oversample. You get more bang for the buck than just filtering away noise above bandwidth of interest. It does required that you have good filters though because the modulation creates lots of noise above band.

Hopefully we can keep this thread alive even though I suppose we have answered the OP

8. Apr 22, 2013

### the_emi_guy

Hey, good topic folks! Maybe we should move this back to EE forum, this is something I have pondered.

Generally when I see noise levels in the millivolts or hundreds of microvolts caused by thermal noise I am dealing with both wide bandwidth and high gain. The unity gain ADC front end amp couldn't possibly have poor enough thermal noise figure to add hundreds of microvolts of noise could it?

Consider the AD10200 (Analog Devices, 12-bit, first one on their list). This is a 250MHz bandwidth part with 50 ohm input.

Theoretical SNR due to 12-bit quantization (SQNR) in dB below full scale is 74dBFS or 0.14mVrms of noise.

Advertized SNR = 67dBFS = 0.32mVrms.

Thus there is 0.18mVrms of noise in excess of quantization noise, or -62dBm.

If we assume that this is thermal noise, and that the device has 250MHz bandwidth, than this is
-86dBm/1Hz. This is 88dB above the thermal noise floor of -174dBm/Hz.

In other words this part's analog front end would have to have a noise figure of 88dB against thermal noise even though it has no gain! Even a crappy unity gain voltage feedback OP amp with large resistor values would have noise figure below 50dB.

I suspect that the excess noise in the SNR spec is due to other impairments such as clock jitter.

We generally use sigma delta modulation in cases where have excess bandwidth and can oversample. You get more bang for the buck than just filtering away noise above bandwidth of interest. It does required that you have good filters though because the modulation creates lots of noise above band.

Hopefully we can keep this thread alive even though I suppose we have answered the OPs question. It is of interest to me and I definitely value others inputs.

9. Apr 22, 2013

### carlgrace

I think knowing a little bit of what is under the hood of a Nyquist ADC could really help you make sense of it. First off, the limitation is not jitter in these ADCs. Most high-performance part have an on-chip PLL that cleans the jitter from the reference clock or it specifies a clean clock signal as part of the ADC support circuits. The noise issue is due ti the front-end sampling network of the ADC.

Basically, ADCs like the part you mentioned (AD10200) use a pipeline architecture, meaning they comprise several identical (or similar) conversion stages. Each stage uses a two-phase non-overlapping clock and a switched-capacitor sampling network. In the first phase, the input is sampled on some capacitors, and in the second phase, this held input is amplified and sampled by the next stage. The issue is with these capacitors.

When you sample a voltage onto a capacitor, there is a thermal noise associated with the sampling with a variance of kT/C where C is the value of the sampling capacitor. It is independent of the series resistance because while the resistor provides the noise (ideal caps are noiseless) the R in the denominator cancels the R in the numerator because the R both generates noise and sets the bandwidth.

Therefore, the noise will be limited by kT/C unless you make the capacitors big enough. However, if you make your capacitors larger it will take more power for your stages to settle in a given time.

So, Nyquist ADC designs are a compromise. They could theoretically be made quantization-noise limited but the market generally doesn't pay for that, so the noise is set at an acceptable level which reduces power consumption and cost. Fitness to purpose.

To get a bit more quantitative, notice that since the noise variance (or power) on a capacitor is kT/C, the rms voltage noise is sq-root(kT/C). That means to reduce the noise voltage by X, you need to increase your capacitor size by X^2. To first order, the power is proportional to the capacitance so the power also increases by X^2.

Therefore, for the AD10200 to reduce its input referred noise to 14 mVrms would require a 4X increase in power consumption! Even then the overall noise wouldn't be 74 dB. Since thermal noise and quantization noise add in quadrature (assuming the input is "busy enough") if the quantization noise were equal to the thermal noise, then the SNR would be degraded by 3 dB to give 71 dB. OUCH!

You can see why commercial ADCs have better linearity than their noise specs.

Also, in case you're interested, this is an IF sampler meaning it is intended for use to sample the Intermediate Frequency of a superhet receiver (obviously the ADC is general purpose, but that's where the spec comes from). In that case, the desired channel is narrowband and the SNR can be greatly improved through the use of a sharp digital bandpass filter downstream of the ADC.

The linearity is key, though, because you don't want intermodulation distortion blocking channels.

So for an RF receiver, typically, linearity is paramount and noise performance is relaxed.

10. Apr 22, 2013

### the_emi_guy

Carlgrace: Thanks for this!

I never thought to consider kT/C noise. 1pf is already 64uV!