State diagram of 4 connected d flip flops

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The discussion centers on creating a state diagram for a circuit consisting of three connected D flip-flops. Participants clarify that with three flip-flops, there are eight possible states (from [000] to [111]), and each state represents the collective state of the flip-flops. The importance of the clock pulse (CP) is emphasized, as state changes occur only on the rising edge of the clock. The conversation concludes with guidance on simplifying the state diagram by removing unnecessary annotations and focusing on the essential state transitions.

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For the 3 states (00, 01, and 10) that you show, what does each of the 2 bits represent?

[edit: I count only 3 flip-flops, not 4 as your problem's title claims]
 
first two bits are the first the first flip flop and so on.
My mistake it should be 3 not 4, its a typo.
 
If you have 3 flip-flops, why not 3 bits?
 
You are making me a bit confused. Are you asking me or telling me?
I'm really lost I have no idea what I should do.
 
It's pretty much incorrect. When you have 3 flip-flops, you have 3 memory elements each capable of being in a 0 or 1 state. The state of this system refers to the collective state of the individual flip-flops. With 3 flip-flops, you have 23 possible system states. The 3-bit value you are showing in the center of the circles represents the state of the flip-flops for that particular system state. For example, when the state of the first flip-flop (going from left to right) is a 1 (internally, not referring to Q or Q') and the second and third are both 0, you can say that the state of the system is [D1, D2, D3] = [1,0,0] or even "4" if you treat [1,0,0] like 1002.

[Edit: I see you are treating the clock like an input to the system. Technically, it is an input but it is a special input used for synchronizing the inputs and allowing the system to advance from state to state. In this case, your "input" is really the output of D3 fed back to D1. I say "input" with quotations because it is really an internal signal, not coming from outside the system.]
 
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To begin with I should have 8 circles(0-7) with 3 bits in each?
At the beginning the "system" is 000 then 001 and so on?
 
You could start with 8 circles. Remember there are 8 possible states. You may not get to some of them. Yes, start with state [000], the implied power-on reset condition.

Be clear in what [000] represents. For purposes of this discussion use [state-of-D1, state-of-D2, state-of-D3] with D1 the FF on the left and D3 the FF on the right.

If you start out with [000] and hit it with a clock pulse, what is the next state?
 
  • #10
I'm sorry but I don't understand this sentence.
"For purposes of this discussion use [state-of-D1, state-of-D2, state-of-D3] with D1 the FF on the left and D3 the FF on the right."

The next state should be [001] if the CP=1. Should I allays assume that the CP is 1?
 
  • #11
I think I'm going to going to change my answer to [100] for state two.
 
  • #12
ogward said:
I'm sorry but I don't understand this sentence.
"For purposes of this discussion use [state-of-D1, state-of-D2, state-of-D3] with D1 the FF on the left and D3 the FF on the right."
Sorry, this was just to make it easy to understand each other. Since the original circuit has no reference designators on any of the flip-flops (FFs), I thought it would be a good idea to name each FF D1, D2, D3, going left to right.
The next state should be [001] if the CP=1. Should I allays assume that the CP is 1?
If you are using the above convention, you are not correct. Let's assume the FFs change state upon the rising edge of the CP (when going from 0 to 1). That is what I meant by "hitting it with a clock pulse"-- a 0-1-0 pulse contains the rising edge).

When in state [000], what do you have for the inputs to each FF? (before any CP happens)Edit-- [100]: then you are correct! Continue the process with each additional CP.
 
  • #13
lewando said:
When in state [000], what do you have for the inputs to each FF? (before any CP happens).

then every FF has to be [000]?
 
  • #14
I thought you were getting on the right track when you correctly asserted [100] as the next state from [000]. How did you get [100]?
 
  • #15
I find it a bit hard to explain but the 1 pushes the [000] to the right so the zero to the right "falls out".
sounds weird when I read what I just wrote...
 
  • #16
Yes, sounds weird :smile:. Let's formalize the action. You need to look at the input to each FF before the CP happens (when in state [000], what are they?). When the CP happens, the state of the input into each FF determines the new state of each FF.

Edit: In the case of a D FF, if the input is a 1 when the CP happens, the new state will be a 1 (with Q = 1 and Q' = 0).
 
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  • #17
If the first state is [000] then something tells me that the inputs should be [D1, D2, D3]= [100]
 
  • #18
I think I'm starting to get this, or at least I hope so...
If in state [000] and receive a 0 I stay in [000], If I get 1 i go to state [100].
If I'm in state [100] and get 0 I stay in [100], if I get 1 I go to state [011].
When in [011] and receive 0 I stay and if I get 1 I go back to state [100].
Is that correct? if so, what's the next step?
 
  • #19
If the first state is [000] then something tells me that the inputs should be [D1, D2, D3]= [100]
This is correct.
If in state [000] and receive a 0 I stay in [000], If I get 1 i go to state [100].
Okay so far.
If I'm in state [100] and get 0 I stay in [100], if I get 1 I go to state [011].
Not so. Similar question: If you are in state [100] (and the clock is 0--no CP) what are the inputs to each FF?
 
  • #20
lewando said:
Not so. Similar question: If you are in state [100] (and the clock is 0--no CP) what are the inputs to each FF?

Aren't they the same as before [100]?
 
  • #21
Aren't they the same as before [100]?
No, they change.

State [000] had inputs to each FF of {100}. A CP happened resulting in the next state of [100]. When in state [100]:
D1 is in a state of 1 (Q = 1, Q' = 0)
D2 is in a state of 0 (Q = 0, Q' = 1)
D3 is in a state of 0 (Q = 0, Q' = 1)

From this information can you determine what the inputs are to each FF, when in state [100]?
 
  • #22
I would have to say [101].
 
  • #23
No, don't guess. Show your reasons if not a guess.
 
  • #24
D1=1, D2=0 and D3=0 ( but it should be inversed which makes it 1)
therefor
[101].
 
  • #25
D1=1, D2=0 and D3=0 ( but it should be inversed which makes it 1)
therefor
[101].
Not following you. Let's go through this carefully.

When in state [100], the Q3' output is 1 which is connected to the D1 input. So the D1 input is 1.

When in state [100], the Q1 output is 1 which is connected to the D2 input. So the D2 input is 1.

When in state [100], the Q2 output is 0 which is connected to the D3 input. So the D3 input is 0.

So, when in state [100] the input to the FFs is {110}, using braces to indicate input, vs state.

Does this make sense?
 
  • #26
It makes sense if the following is true.
when in state [110] the input to the FFs is (111).

What about if CP is 0? should I do something?
For some reason I want to stand in the currant state if CP is 0.
 
  • #27
ogward said:
It makes sense if the following is true.
when in state [110] the input to the FFs is (111).

That is true. You are on the right track.

What about if CP is 0? should I do something?
For some reason I want to stand in the currant state if CP is 0.
When the clock is 0, you are correct--you stay in current state. In reality, "D" flip-flops are designed to change state only when the rising edge of the clock signal happens. [EDIT: please understand: they don't have to change state... if the D input is not changing then the output will not change no matter how many rising edges happen on the clock input]. The "rising edge" occurs as the clock transitions from a 0 to a 1. Not to confuse you, but even when the clock is a 1 you stay in your current state.
 
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  • #28
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  • #29
The state transitions look right and there are 2 unused states. Good work by you :smile:!

The only thing that is bothering me is that the circuit of original problem does not really have any inputs (or outputs) from/to the outside world, that is. Is I said in a prior post, the clock is a special input and it usually (in fact always) is not shown in state transition diagrams. It is assumed to be occurring at some random or periodic rate so you don't have to show it. Basically (EDIT: for this problem), whenever there is a clock rising edge, a change of state will occur.
 
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  • #30
I got to go soon so let me say this: based on the fact that there is no external input for this circuit and that clock transitions are assumed for these diagrams, I would advise eliminating the "stay-in-the-same-state" paths and also get rid of the "1" annotation on the transition paths.

Best regards.
 

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