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Problems with EE homework dealing with Octal D-FF and D Latch

  • Thread starter s w
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  • #1
s w
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Homework Statement


Show the timing diagrams of the input bus and control inputs so the D Flip Flop has the value AA and the D-Latch has the value 55.
[PLAIN]http://img89.imageshack.us/img89/5047/babykg.jpg [Broken]

The timing diagram consists of all the inputs, OE1, WR1, OE2, and WR2.

Homework Equations


NONE

The Attempt at a Solution


I mainly don't understand the purpose of OEN. I know that the latch will output the input when G is 1, and the flip flop will output on rising edge, but I honestly do not know how to store the data. I know that I must first load 55 into the flip flop, then pass that to the latch and then load in the AA but I am unsure how to actually load the information in. I assume it deals with OEN but I have not found a good explanation for that.
 
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Answers and Replies

  • #2
berkeman
Mentor
57,270
7,262

Homework Statement


Show the timing diagrams of the input bus and control inputs so the D Flip Flop has the value AA and the D-Latch has the value 55.
[PLAIN]http://img89.imageshack.us/img89/5047/babykg.jpg [Broken]

The timing diagram consists of all the inputs, OE1, WR1, OE2, and WR2.

Homework Equations


NONE

The Attempt at a Solution


I mainly don't understand the purpose of OEN. I know that the latch will output the input when G is 1, and the flip flop will output on rising edge, but I honestly do not know how to store the data. I know that I must first load 55 into the flip flop, then pass that to the latch and then load in the AA but I am unsure how to actually load the information in. I assume it deals with OEN but I have not found a good explanation for that.
OEN is just the Output Enable. From the description of the problem, I would think you could keep the outputs enabled all the time for this problem. If you had two chips' outputs connected together, both feeding into one other chip's inputs, then you would need to control the OEN inputs of the two chips to keep them from fighting each other on their outputs. But as this circuit is just connected 1-to-1, I think you can just keep the OENs asserted.
 
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  • #3
s w
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Thanks for the reply. I think I figured out multiple ways to do it actually. Like you said, I could keep OEN at 0 all the time, well actually in this case wouldnt it be '1' since there is the not on the OEN?? Well, if I kept OEN enabled then I would just set G to 0 once it has the 55 loaded into it. Or I could keep G at 1 and then change the OEN1 to disabled once the 55 is loaded in to the latch. Is this correct?

Actually I really want to know is, should OE1 and OE2 be 1 or 0 for this problem, given the 'not'.
 
  • #4
berkeman
Mentor
57,270
7,262
Thanks for the reply. I think I figured out multiple ways to do it actually. Like you said, I could keep OEN at 0 all the time, well actually in this case wouldnt it be '1' since there is the not on the OEN?? Well, if I kept OEN enabled then I would just set G to 0 once it has the 55 loaded into it. Or I could keep G at 1 and then change the OEN1 to disabled once the 55 is loaded in to the latch. Is this correct?

Actually I really want to know is, should OE1 and OE2 be 1 or 0 for this problem, given the 'not'.
The circle at the input of the chip schematic figure means that the input is active low, so drive both low to enable their outputs.
 

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