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Hello.
I have been running some simulations on CMOS inverters. When I change the channel dimensions, I noticed something interesting with the drain current -- the smaller the channel dimensions (say around 3μm x 3μm) the simulated drain current is very close to the predicted theory drain current ...but when I change the dimensions to maybe say 15μm x 3μm, the simulated drain current seem to get further away from the predicted current, and even more so when I go to about 20μm x 3μm.
Is there any particular reason for this, or is it just one of those things?
Thanks in advance for any replies, and any ideas.
Slán go fóill
Seán
I have been running some simulations on CMOS inverters. When I change the channel dimensions, I noticed something interesting with the drain current -- the smaller the channel dimensions (say around 3μm x 3μm) the simulated drain current is very close to the predicted theory drain current ...but when I change the dimensions to maybe say 15μm x 3μm, the simulated drain current seem to get further away from the predicted current, and even more so when I go to about 20μm x 3μm.
Is there any particular reason for this, or is it just one of those things?
Thanks in advance for any replies, and any ideas.
Slán go fóill
Seán