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Transistor drain currents and changing width & length sizes

  1. Nov 15, 2011 #1
    Hello.

    I have been running some simulations on CMOS inverters. When I change the channel dimensions, I noticed something interesting with the drain current -- the smaller the channel dimensions (say around 3μm x 3μm) the simulated drain current is very close to the predicted theory drain current ....but when I change the dimensions to maybe say 15μm x 3μm, the simulated drain current seem to get further away from the predicted current, and even more so when I go to about 20μm x 3μm.

    Is there any particular reason for this, or is it just one of those things?

    Thanks in advance for any replies, and any ideas.

    Slán go fóill
    Seán
     
  2. jcsd
  3. Nov 15, 2011 #2

    es1

    User Avatar

    How are you predicting the current and what model type are you using for the MOSFETs?

    There are many models that have various trade-offs. In fact, Hspice even has a whole manual on it.
    http://www.ece.tamu.edu/~spalermo/ecen474/hspice_mosfet.pdf

    I haven't gotten into model creation much myself but I know it is tricky. As for DC and larger FETs (I think 20x3 would be fairly big) many vendors just resort to using passives to make the FET curves match the measured data. This is for a board level power transistor though. Not sure what is done for transistors in an IC. Probably they just make another model... :)

    Here is an example of a board transistor FET model from Diodes Inc. It matches the data sheet nominal curves very nicely.


    *---------- DMN3110S Spice Model ----------
    .SUBCKT DMN3110S 10 20 30
    * TERMINALS: D G S
    M1 1 2 3 3 NMOS L = 1E-006 W = 1E-006
    RD 10 1 0.01593
    RS 30 3 0.001
    RG 20 2 1.4
    CGS 2 3 2.711E-010
    EGD 12 0 2 1 1
    VFB 14 0 0
    FFB 2 1 VFB 1
    CGD 13 14 5.2E-010
    R1 13 0 1
    D1 12 13 DLIM
    DDG 15 14 DCGD
    R2 12 15 1
    D2 15 0 DLIM
    DSD 3 10 DSUB
    .MODEL NMOS NMOS LEVEL = 3 VMAX = 5.378E+005 ETA = 0.001 VTO = 2.227
    + TOX = 6E-008 NSUB = 1E+016 KP = 9.816 U0 = 400 KAPPA = 10
    .MODEL DCGD D CJO = 2.317E-010 VJ = 0.2783 M = 0.4405
    .MODEL DSUB D IS = 1E-015 N = 0.8731 RS = 0.04482 BV = 35 CJO = 1.086E-011 VJ = 0.4101 M = 0.9
    .MODEL DLIM D IS = 0.0001
    .ENDS
    *Diodes DMN3110S Spice Model v1.0 Last Revised 2011/8/15
     
  4. Nov 15, 2011 #3
    Hello,

    And thanks for the reply.

    I am using a package called OrCAD for the simulation side of things, and to get the drain current. the equation

    Id = (μ0 W Cox/L)(Vgs - Vt)2

    I don't know too much about the design of the transistor, but here was the parameters we have been given

    .
    MODEL CMOSN NMOS ( LEVEL = 7
    +TNOM = 27 TOX = 3.13E-8
    +XJ = 3E-7 NCH = 7.5E16 VTH0 = 0.5797266
    +K1 = 0.9292755 K2 = -0.0671781 K3 = 7.3222642
    +K3B = -1.7415465 W0 = 2.400263E-7 NLX = 1E-8
    +DVT0W = 0 DVT1W = 0 DVT2W = 0
    +DVT0 = 0.9683013 DVT1 = 0.3162433 DVT2 = -0.1832987
    +U0 = 676.4613491 UA = 1.893878E-9 UB = 1.237595E-18
    +UC = 4.356663E-11 VSAT = 1.076176E5 A0 = 0.6202983
    +AGS = 0.1273117 B0 = 2.444181E-6 B1 = 5E-6
    +KETA = -4.531088E-3 A1 = 0 A2 = 1
    +RDSW = 3E3 PRWG = -0.0526839 PRWB = -0.0433742
    +WR = 1 WINT = 1.560646E-7 LINT = 1.673752E-7
    +XL = 0 XW = 0 DWG = -1.907911E-8
    +DWB = 3.616754E-8 VOFF = -0.0106438 NFACTOR = 0.6793951
    +CIT = 0 CDSC = 0 CDSCD = 0
    +CDSCB = 0 ETA0 = -1 ETAB = -0.4894254
    +DSUB = 0.9972946 PCLM = 1.2573744 PDIBLC1 = 9.514253E-3
    +PDIBLC2 = 1.868855E-3 PDIBLCB = -0.1 DROUT = 0.0636553
    +PSCBE1 = 2.188583E9 PSCBE2 = 5.00045E-10 PVAG = 0.1815139
    +DELTA = 0.01 RSH = 54 MOBMOD = 1
    +PRT = 0 UTE = -1.5 KT1 = -0.11
    +KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
    +UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
    +WL = 0 WLN = 1 WW = 0
    +WWN = 1 WWL = 0 LL = 0
    +LLN = 1 LW = 0 LWN = 1
    +LWL = 0 CAPMOD = 2 XPART = 0.5
    +CGDO = 1.77E-10 CGSO = 1.77E-10 CGBO = 1E-10
    +CJ = 2.868956E-4 PB = 0.9804319 MJ = 0.5196841
    +CJSW = 1.184497E-10 PBSW = 0.9673454 MJSW = 0.1
    +CJSWG = 6.4E-11 PBSWG = 0.9673454 MJSWG = 0.1
    +CF = 0 )
    .MODEL CMOSP PMOS ( LEVEL = 7
    +VERSION = 3.1 TNOM = 27 TOX = 3.13E-8
    +XJ = 3E-7 NCH = 2.4E16 VTH0 = -0.8476404
    +K1 = 0.4513608 K2 = 2.379699E-5 K3 = 13.3278347
    +K3B = -2.2238332 W0 = 9.577236E-7 NLX = 1E-8
    +DVT0W = 0 DVT1W = 0 DVT2W = 0
    +DVT0 = 0.7754903 DVT1 = 0.3327119 DVT2 = -0.1506274
    +U0 = 236.8923827 UA = 3.833306E-9 UB = 1.487688E-21
    +UC = -1.08562E-10 VSAT = 1.229793E5 A0 = 0.4180432
    +AGS = 0.2425542 B0 = 2.927404E-6 B1 = 1.743455E-6
    +KETA = -9.827469E-3 A1 = 0 A2 = 0.364
    +RDSW = 2.509041E3 PRWG = 0.066585 PRWB = -0.0993304
    +WR = 1 WINT = 1.565065E-7 LINT = 1.37056E-7
    +XL = 0 XW = 0 DWG = -2.13917E-8
    +DWB = 3.857544E-8 VOFF = -0.0877184 NFACTOR = 0.2508342
    +CIT = 0 CDSC = 2.924806E-5 CDSCD = 1.497572E-4
    +CDSCB = 1.091488E-4 ETA0 = 0.15903 ETAB = -1.22988E-3
    +DSUB = 0.2873 PCLM = 3.8183576 PDIBLC1 = 0
    +PDIBLC2 = 1E-3 PDIBLCB = -9.985049E-4 DROUT = 0.0189734
    +PSCBE1 = 3.329215E9 PSCBE2 = 1.070858E-5 PVAG = 11.9390264
    +DELTA = 0.01 RSH = 75.6 MOBMOD = 1
    +PRT = 0 UTE = -1.5 KT1 = -0.11
    +KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
    +UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
    +WL = 0 WLN = 1 WW = 0
    +WWN = 1 WWL = 0 LL = 0
    +LLN = 1 LW = 0 LWN = 1
    +LWL = 0 CAPMOD = 2 XPART = 0.5
    +CGDO = 2.3E-10 CGSO = 2.3E-10 CGBO = 1E-10
    +CJ = 2.92294E-4 PB = 0.745213 MJ = 0.4283132
    +CJSW = 1.512911E-10 PBSW = 0.99 MJSW = 0.1015527
    +CJSWG = 3.9E-11 PBSWG = 0.99 MJSWG = 0.1015527
    +CF = 0 )​

    If you can make heads or tails of that!

    Do you think that the difference as the sizes get bigger could be down to the modle parameters?

    As for the 20x3, yea, I know that was big, I was just playing around with different things.

    Thanks again.
    Seán
     
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