Understanding CMOS Gate States: Shoot-Through and Capacitance Effects

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Discussion Overview

The discussion revolves around the behavior of CMOS gate states, specifically focusing on the concepts of shoot-through and capacitance effects in pull-up and pull-down networks. Participants explore the implications of these states during transitions between logical values and their impact on power dissipation and supply bounce.

Discussion Character

  • Technical explanation, Conceptual clarification, Debate/contested

Main Points Raised

  • One participant asks for clarification on pull-up and pull-down networks in relation to CMOS gates.
  • Another participant suggests that replacing networks with single FETs generally leads to steady states of 1 or 0, but notes that slow transitions can result in other states like Z or crowbarred, depending on threshold voltages.
  • A participant expresses confusion regarding the previous explanations.
  • It is mentioned that a crowbarred state occurs during transitions between logical states, contributing to power dissipation in CMOS and causing supply bounce.
  • One participant elaborates that the crowbar state, referred to as "shoot-through," is a source of current consumption in CMOS, alongside the effects of charging and discharging gate and net capacitances. They note that the significance of shoot-through depends on the threshold and supply voltages, indicating that both devices can be on simultaneously under certain conditions.

Areas of Agreement / Disagreement

Participants express varying levels of understanding and agreement on the implications of shoot-through and capacitance effects, indicating that multiple views and some confusion remain regarding the concepts discussed.

Contextual Notes

The discussion does not resolve the complexities of how threshold voltages influence the behavior of CMOS gates during transitions, nor does it clarify the specific conditions under which shoot-through becomes significant.

anhnha
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Please help me with the question in the picture about pull-up and pull-down networks.

attachment.php?attachmentid=69451&stc=1&d=1399337661.png
 

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If your networks are replaced with single FET's, then, in general, yes, for steady state 1 or 0 input values.

Even then though, when the input is (slowly) transitioning between 0 and 1 you can get other states (Z or crowbarred), depending on the threshold voltages.
 
Thank you. That was a bit confusing.
 
Also, you always get a crowbarred state for a short time when a logic gate is transitioning between logical states. That is where the power dissipation of CMOS comes from. It is also the source of supply bounce.
 
The short "crowbar" state during logic transitions is referred to as "shoot-through" and is only one source of CMOS current consumption and supply bounce. Another is the charging and discharging of gate and net capacitances. The Shoot-through portion of CMOS current can be very small or very significant depending on threshold and supply voltages. To the extent that the supply and thresholds are such that both devices can be on at the same time, shoot-through will be significant. But the charging and discharging on gate and net capacitances is generally a major contributer.
 

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