Verify 2 Layout Designs: NOR & NAND

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Two layout designs for a 2-input NOR and NAND gate were presented for verification. The designs prioritize functionality over aesthetics, with noted issues regarding snap spacing settings in Cadence. Feedback confirmed that the NAND layout correctly positions series devices at the bottom and parallel devices at the top, while the NOR layout has parallel devices at the bottom and series devices on top. The designs are deemed correct, allowing the creator to proceed with the larger layout. Overall, the discussion emphasizes the importance of verifying smaller components in circuit design.
Maxwell
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Hey, I was wondering if anyone would be able to verify if two of my layouts are correct. These are going to be part of a larger layout, so I want to make sure the smaller pieces are correct before I move on.

Please excuse to ugly design - I'm not too worried about aesthetics right now - just functionality. Some of my pieces may not be symmetrical because Cadence does not save my snap spacing settings, so every time I open a design, I have to remember to change it to my preferred values. :rolleyes:

Thanks.

2 Input NOR

http://img.photobucket.com/albums/v220/Monstrosity/NOR.jpg" 2 Input NAND:

http://img.photobucket.com/albums/v220/Monstrosity/NAND.jpg"
 
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They look correct. The NAND has the series devices at the bottom, and the parallel devices at the top. The NOR has the parallell devices at the bottom and the series devices on the top.

- Warren
 
Thanks, chroot.
 
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