Discussion Overview
The discussion revolves around VLSI testing, specifically focusing on fault models and test circuits. Participants seek clarification on the relationship between these concepts and explore examples of test circuits used in VLSI testing methodologies.
Discussion Character
- Exploratory, Technical explanation, Conceptual clarification
Main Points Raised
- One participant expresses confusion about whether fault models and test circuits are the same or different, indicating a need for clarification.
- Another participant shares a presentation link that outlines various fault models and testing methodologies, such as Built-In Self-Test (BIST) and boundary scan.
- A participant describes a process where a test circuit is created to inject a fault, such as an input being stuck at zero, and explains how this is used to determine if the circuit under test fails based on the output signal.
Areas of Agreement / Disagreement
Participants do not appear to reach a consensus on the relationship between fault models and test circuits, and the discussion remains unresolved regarding this distinction.
Contextual Notes
Some participants reference specific slides from the shared presentation, but the understanding of fault models and test circuits remains unclear, indicating potential limitations in definitions and assumptions.