# Voltage Divider Bias Under Load

Hey, I'm kinda stuck in this odd question. I've tried searching on the Internet but haven't found much help.

Basically, I have a voltage divider biased transistor. I can solve and find its Q-point without an external load, but I'm kinda confused how the circuit will change when there is an external load attached to it. The load is connected between the collector resistor and the collector terminal.

There ought to be a reduction in Emitter current, right? Will Collector current still be approximately equal to Emitter current?

Any help would be appreciated.

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berkeman
Mentor
Hey, I'm kinda stuck in this odd question. I've tried searching on the Internet but haven't found much help.

Basically, I have a voltage divider biased transistor. I can solve and find its Q-point without an external load, but I'm kinda confused how the circuit will change when there is an external load attached to it. The load is connected between the collector resistor and the collector terminal.

There ought to be a reduction in Emitter current, right? Will Collector current still be approximately equal to Emitter current?

Any help would be appreciated.
Thread moved from EE to homework help.

You're saying that the load is connected in series with the collector resistor Rc? Then it just increases the value of Rc effectively. The emitter current would generally be set by an Re resistor (often bypassed with a capacitor for higher gain at AC), and the base bias voltage divider. Does that help?

No, I meant the load is in parallel with the collector. One terminal of the load (RL) is connected between Rc and and the collector terminal. The other terminal of RL is grounded. So effectively, it has Vc across it.

What I want to know how do I calculate the various voltages and currents in such a circuit? What changes would such a load introduce?

I also realize if the resistance of the load is not very large as compared to Voltage Divider Bias then there will be a reduction of IC(SAT). That is basically the transistor will reach its saturation point more quickly. Does that make sense or am I way off the mark?

If it does, could you please tell me why that happens?

I also had another question, suppose I want to design a VDB circuit and have been provided a Q point that I need to set using resistors in the VD. What I was confused about is how do I select Rc? I've noticed most texts select Rc as to drop half of Vcc across it. Why is that?

PS: Thank you for moving my thread. First time here, didn't know where to put it.

berkeman
Mentor
You bias the NPN in CE configuration by setting Ic with the Vb and Re values (with small corrections -- Quiz Question #1 -- what are those?), and you typically bypass Re with a capacitor to increase the AC voltage gain in your signal passband (Quiz Question #2 -- what is the voltage gain Av of a CE amplifier?).

You bias Vc to about half of the supply Vcc, because you want to get the best and most symmetric large signal gain through the amp, so you want to clip at top and bottom of the output waveform fairly symmetrically. Quiz Question #3 -- to get the most symmetric clipping, would you bias Vc slightly above or below Vcc/2? Why?

http://en.wikipedia.org/wiki/Common_emitter

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2 - Av = - RC/RE (if i'm not mistaken)
3 - I would bias it slightly below Vcc/2 as that would clip the signal because the 'allowable voltage' (voltage that can pass through without clipping) would be lower then set by Av... and so the signal would be clipped. I hope that makes sense.

Thanks again

berkeman
Mentor
-1- One correction has to do with Ic not equal to Ie (by how much?). Another has to do with the difference between Vb and Ve (by how much? and what about temperature?).

-2- The Av you list is basically correct. What effect does a cap around the explicit Re have? What is the Av at freqs above Re*Ce? What things limit Av to some maximum?

-3- To center the output swing, look at how high the output can go (when the transistor is cutoff), and how low the output can go (when the transistor is in saturation). What's the midpoint of those two voltages?

-1- One correction has to do with Ic not equal to Ie (by how much?). Another has to do with the difference between Vb and Ve (by how much? and what about temperature?).
Ie is slighty greater then Ic. Ie = Ic + Ib. Vb = 0.7 + Ve. So there's a 0.7 V difference.

Temperature would affect beta.

-2- The Av you list is basically correct. What effect does a cap around the explicit Re have? What is the Av at freqs above Re*Ce? What things limit Av to some maximum?
A capacitor would increase the gain of the AC signal as it would allow it to bypass Re (which reduces gain).

Don't know about your other questions. I haven't really studied CE amplifier yet in my class, we've only studied different transistor biasing. And I'm (still) confused about to how to calculate the voltage across the load when its connected to the output of a VDB configuration... The load is just a resistor.

-3- To center the output swing, look at how high the output can go (when the transistor is cutoff), and how low the output can go (when the transistor is in saturation). What's the midpoint of those two voltages?
That would be (Vcc - Ve)/2

Right?

berkeman
Mentor
Good job. The temperature also affects the Vbe voltage drop -- you get about 0.7V at room temperature, and 0.6V or less as the temperature goes up. The tempco for BJTs and diodes is about -2.1mV/degree C, IIRC.

As to the effect of the load resistor, it just changes the output voltage some, according to the resistor value. The output impedance of the amp is Rc//Z (where Z is the dynamic output impedance of the transistor), so as the load resistance gets smaller, it loads the output of the CE stage more and more. To compensate, you can increase Ic (lower Re), and lower Rc, but then you are burning more quiescent power. That's a general situation that you encounter with amplifiers -- as you need to drive lower impedance loads, you need to increase your quiescent power point, and waste more power in the amp itself.

One more question, regarding voltage drop across Rc... you mentioned that I need to drop Vcc/2 on Rc to get the most symmetrical voltage gain, right?

But wouldn't that be the case if there is no emitter resistance? If there is an em-miter resistance I would need to center the output wave differently, by using (Vcc-Ve)/2?

Am I on the right track?

berkeman
Mentor
One more question, regarding voltage drop across Rc... you mentioned that I need to drop Vcc/2 on Rc to get the most symmetrical voltage gain, right?

But wouldn't that be the case if there is no emitter resistance? If there is an em-miter resistance I would need to center the output wave differently, by using (Vcc-Ve)/2?

Am I on the right track?
Yes. But what function does Re serve? If it lowers the voltage gain and narrows the output dynamic range, why do we use it?

It gives us stability!!! :D

berkeman
Mentor
It gives us stability!!! :D
Well, yes, it's true that the emitter degeneration resistor Re does add some stability to the CE configuration, but I was thinking more in terms of bias stability.....