Voltage divider rule for CMOS in 0-state and leakage current

[jaus tail]

Homework Statement

Voltage divider rule for CMOS

Relevant Equations

Voltage across R1 is Vsupply * (R1)/ (R1 + R2)

I use the voltage divider rule as output voltage = Voltage across R1 = 5 * ( 0.5 / (0.5 + 20) )
This comes as 0.122 V
I'm not sure why they've mentioned I leakage and does 0-state have any impact on answer.

 

[NascentOxygen]

If that is supposed to represent a CMOS logic gate in 0-state, they haven't used a very representative value for the FET's typical OFF resistance, 20 kΩ!

 

[jaus tail]

They haven't mentioned anything else apart from the question. I think the FET will act as simple voltage divider.

 

[NascentOxygen]

Yes, the FETs form a voltage divider. But if the OFF FET was a more reasonable value (let's say, 20 MΩ) then you can see how a small leakage current could upset the resistive divider.

 

[DaveE]

Yes, I agree the question is confusing, poorly written. You've done all you can with the data you have.

 

[jaus tail]

Yes, the FETs form a voltage divider. But if the OFF FET was a more reasonable value (let's say, 20 MΩ) then you can see how a small leakage current could upset the resistive divider.

Well if the FET had very high resistance, then I guess there wouldn't be any drop across it. Leakage current would be zero as it's like an open circuit. So voltage would be 5 V

 

[Tom.G]

Well if the FET had very high resistance, then I guess there wouldn't be any drop across it.

Uhmm, would you like to re-think that statement?
If so, please be specific as to which FET is referenced where. "the" and "it" are ambiguous.

 

[jaus tail]

Uhmm, would you like to re-think that statement?
If so, please be specific as to which FET is referenced where. "the" and "it" are ambiguous.

If the FET has very high resistance (both FET in series), the resistance of the path becomes very high and resistance will oppose any current. Unless the current is being forced to flow through it. In that case the voltage would be very high.
But even then the Vss will split as per the voltage divider rule. I don't think leakage current plays any role here as Vss supersedes it.

 

[Tom.G]

Unless the current is being forced to flow through it.

Doesn't V_ss do that?

The leakage current is defined as the current thru the supposedly "Off" FET, Q2. (poor analogy, but like a leaky faucet that drips)

Problem Statement: Voltage divider rule for CMOS
Relevant Equations: Voltage across R1 is Vsupply * (R1)/ (R1 + R2)

I'm not sure why they've mentioned I leakage and does 0-state have any impact on answer.

The circuit given is a simplification of the output stage of a CMOS logic device. The 0-state reference would be to indicate that the output voltage should be a logic LOW level. The reference to I_leakage points out that devices in their Off state have a high but finite resistance, allowing a little bit of current to flow. The example circuit given has exaggerated the resistance of the supposedly Off FET to be a lower value than is commonly found.

I agree with your original approach and answer of 0.122V.

Hope this helps.

Cheers,
Tom

 

[jaus tail]

Thanks :)