Voltage divider rule for CMOS in 0-state and leakage current

In summary, the voltage divider rule applies when the FETs in the circuit are in their "Off" state, and the voltage across R1 is the voltage supplied * (R1)/(R1+R2). If the FETs had very high resistance, then the resistance of the path would become very high and current would not flow. However, the Vss would still split as per the voltage divider rule.
  • #1
jaus tail
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Homework Statement
Voltage divider rule for CMOS
Relevant Equations
Voltage across R1 is Vsupply * (R1)/ (R1 + R2)
245653

I use the voltage divider rule as output voltage = Voltage across R1 = 5 * ( 0.5 / (0.5 + 20) )
This comes as 0.122 V
I'm not sure why they've mentioned I leakage and does 0-state have any impact on answer.
 
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  • #2
If that is supposed to represent a CMOS logic gate in 0-state, they haven't used a very representative value for the FET's typical OFF resistance, 20 kΩ!
 
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  • #3
They haven't mentioned anything else apart from the question. I think the FET will act as simple voltage divider.
 
  • #4
Yes, the FETs form a voltage divider. But if the OFF FET was a more reasonable value (let's say, 20 MΩ) then you can see how a small leakage current could upset the resistive divider.
 
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  • #5
Yes, I agree the question is confusing, poorly written. You've done all you can with the data you have.
 
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  • #6
NascentOxygen said:
Yes, the FETs form a voltage divider. But if the OFF FET was a more reasonable value (let's say, 20 MΩ) then you can see how a small leakage current could upset the resistive divider.
Well if the FET had very high resistance, then I guess there wouldn't be any drop across it. Leakage current would be zero as it's like an open circuit. So voltage would be 5 V
 
  • #7
jaus tail said:
Well if the FET had very high resistance, then I guess there wouldn't be any drop across it.
Uhmm, would you like to re-think that statement?
If so, please be specific as to which FET is referenced where. "the" and "it" are ambiguous.
 
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  • #8
Tom.G said:
Uhmm, would you like to re-think that statement?
If so, please be specific as to which FET is referenced where. "the" and "it" are ambiguous.
If the FET has very high resistance (both FET in series), the resistance of the path becomes very high and resistance will oppose any current. Unless the current is being forced to flow through it. In that case the voltage would be very high.
But even then the Vss will split as per the voltage divider rule. I don't think leakage current plays any role here as Vss supersedes it.
 
  • #9
jaus tail said:
Unless the current is being forced to flow through it.
Doesn't Vss do that?

The leakage current is defined as the current thru the supposedly "Off" FET, Q2. (poor analogy, but like a leaky faucet that drips)

jaus tail said:
Problem Statement: Voltage divider rule for CMOS
Relevant Equations: Voltage across R1 is Vsupply * (R1)/ (R1 + R2)

I'm not sure why they've mentioned I leakage and does 0-state have any impact on answer.
The circuit given is a simplification of the output stage of a CMOS logic device. The 0-state reference would be to indicate that the output voltage should be a logic LOW level. The reference to Ileakage points out that devices in their Off state have a high but finite resistance, allowing a little bit of current to flow. The example circuit given has exaggerated the resistance of the supposedly Off FET to be a lower value than is commonly found.

I agree with your original approach and answer of 0.122V.

Hope this helps.

Cheers,
Tom
 
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  • #10
Thanks :)
 
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Related to Voltage divider rule for CMOS in 0-state and leakage current

1. What is the purpose of the voltage divider rule for CMOS in 0-state?

The voltage divider rule for CMOS in 0-state is used to determine the voltage distribution between two resistors in series. This is important in CMOS circuits as it helps to maintain a stable voltage level and ensure proper functioning of the circuit.

2. How does the voltage divider rule help to reduce leakage current in CMOS circuits?

The voltage divider rule helps to reduce leakage current in CMOS circuits by ensuring that the voltage across each resistor is equal. This means that the leakage current will also be evenly distributed, reducing its overall impact on the circuit.

3. What factors can affect the accuracy of the voltage divider rule in CMOS circuits?

The accuracy of the voltage divider rule in CMOS circuits can be affected by factors such as temperature, variations in resistor values, and supply voltage fluctuations. These factors can cause deviations from the expected voltage distribution and may need to be taken into account for more precise calculations.

4. Can the voltage divider rule be applied to non-CMOS circuits?

Yes, the voltage divider rule can be applied to non-CMOS circuits as well. It is a general rule that can be used to determine the voltage distribution in any circuit with two resistors in series. However, the specific values of the resistors and other circuit parameters may vary.

5. What are some practical applications of the voltage divider rule in CMOS circuits?

The voltage divider rule is commonly used in CMOS circuits for biasing, level shifting, and voltage regulation. It is also used in the design of analog-to-digital converters, amplifiers, and other electronic devices. Additionally, it can be used to calculate the voltage at different nodes in a circuit, aiding in circuit analysis and troubleshooting.

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