Engineering What is the output for the following logic circuit?

[icesalmon]

Homework Statement

What is the output for the following logic circuit?

Relevant Equations

DeMorgan's Law
Logical Operations involving Logic Gates

I obtained the following result:
([(A xor B) xor 0]* AC)'
([(A'B + AB') xor (0)]*AC)'
[([A'B + AB']*(0)' + 0)*AC)]'
[(A'B + AB')*(1)*(AC)]'
[A'ABC + AB'AC]'
[AB'C]'
A'+B+C'
the solution to this problem is getting a different answer, I don't know why this solution isn't inverting the output AB'C

 

[FactChecker]

I agree with your answer. I think the simplest way to see that the given answer is wrong is to consider how C appears in it. The only appearance of C is as an input to the final NAND. It seems that +C' must be in the correct answer.

 

[eq1]

I think the simplest way to see that the given answer is wrong

I was looking back and forth and at the given answer and wondering if the circuit and the explanation actually even go together. The explanation says the second gate is a NOR and the last gate is an AND but that's not what's drawn.

module problem2;
wire A,B,C,out;
reg [2:0] x;
assign out = !( A & C & (0^(A^B)) );
assign {A,B,C}=x[2:0];
initial begin
  $display("A B C | O");
  x=0;
  do begin
    #1 $display("%b %b %b | %b",A,B,C,out);
    x=x+1;
  end while(x!=0);
end
endmodule

Which yields A'+B+C'

A B C | O
0 0 0 | 1
0 0 1 | 1
0 1 0 | 1
0 1 1 | 1
1 0 0 | 1
1 0 1 | 0
1 1 0 | 1
1 1 1 | 1

 

[icesalmon]

the errata for a study guide I'm using to prepare for the Fundamentals of Engineering Exam didn't include this correction and was issued in 2017 so I decided to ask here. The solution I included corresponded to the problem I posted in the study guide, I'm not sure what happened with the solution to this problem when it was written. But I'm convinced this is a mistake. Thanks for the help in verifying that it was a mistake, i'll just flag the problem and move on.