Why is the PC incremented by 4 for superscalar pipelines?

[Jusamyth]

Hello. I need some help with this question involving Pipelines. Any help would definatley be appreciative.

Why is the PC (Program Counter) is incremented by 4 for a superscalar pipeline which executes TWO instructions at a time

Thanks in Advance!

 

[so-crates]

What architechture ?

 

[Jusamyth]

MIPS assembly language

 

[TenaliRaman]

In MIPS, the program counter counts instructions in "bytes" instead of "instructions". In most implementations, PC<--PC+1 would move to next instruction but in MIPS, PC<--PC+1 moves to next byte.

In MIPS , each instruction is of fixed length of 32 bits or 4 bytes, which probably explains your question.

-- AI

 

[so-crates]

That seems pretty logical. If MIPS is a 16-bit machine its "words" would consist of two bytes, so it has to skip ahead 2 per instruction and not 1.