Why more MHz requires more cooling?

[yoran]

Hi,

I was wondering why a processor is producing more heat when you increase its clock frequency. My idea is that current is sent through the processor at the beginning of each clock cycle. This produces heat and after the current is gone (does it really disappear or is there always current in the circuit?), it needs some time to dissipate its heat. If the next clock signal arrives too soon, it may not have enough time to cool down so the processor is "hotter".
I don't know if this is correct because it assumes that current is available in the circuit only for short amount of times (at each clock signal). Please correct me if I'm wrong.

Thanks.

 

[quadraphonics]

Your intuition is basically correct. Modern CPUs use a form of logic called CMOS, in which current is (ideally) only drawn during changes in the logical state. So, increasing the clock frequency means that you make more state changes per second, and so draw more current per second, and so consume more power, which translates into more heat.

That said, as circuits are miniaturized further and further, the amount of "leakage" current which is drawn at steady state increases, and so the power draw goes up. This factor is becoming more and more important in modern logic designs, although, AFAIK, the total power consumption is still dominated by the transitions.

Also, there are other forms of logic circuits where it the state transitions do not require more power than the steady state, and so the power consumption does not increase greatly with the clock speed. However, the total power drawn by such approaches tends to be much larger than CMOS, and there are other factors that makes them unsuitable for high-speed, high-complexity applications such as microprocessors.

 

[yoran]

Ok thanks for this answer. It's just what I needed to know :).

 

[Phrak]

To suppliment what quadraphonics had to say:
Each gate in a mos (cmos) transistor appears as a small capacitor. With millions of them, the capacitance adds up. The power loss in driving these little caps every clock transition is p=fcv^2, proportional to the frequency.

 

[deakie]

So Phrak, if they could trim the gate widths in those transistors, they could effectively lower the power consumption at the same frequency...or increase the frequency without raising the power beyond what is already available then?