The discussion revolves around the behavior of a D flip-flop circuit, specifically whether an LED will be ON or OFF after a reset is applied. Participants explore the implications of the circuit's design and the function of various inputs, including the RESET line.
Participants do not reach a consensus on the effect of the RESET line or the overall behavior of the circuit. Multiple viewpoints and uncertainties remain regarding the operation of the D flip-flop and its inputs.
There are unresolved questions about the specific function of the RESET line and its interaction with the other inputs. The discussion also reflects varying familiarity with D flip-flops among participants.
cepheid said:Hi physixchic,
What are those two inputs on the D flip flop that aren't D, Q, Q' or clk? They both have negated inputs.
physixchic said:Is it because RESET makes everything a 0 which makes Q a 0 and Q' a 1?
These flip-flops are very useful, as they form the basis for shift registers, which are an essential part of many electronic devices. The advantage of the D flip-flop over the D-type latch is that it "captures" the signal at the moment the clock goes high, and subsequent changes of the data line do not influence Q until the next rising clock edge. An exception is that some flip-flops have a "reset" signal input, which will reset Q (to zero), and may be either asynchronous or synchronous with the clock.
cepheid said:That's plausible, but I don't know for sure, because the D flip flops I'm familiar with don't have those additional inputs:
http://hyperphysics.phy-astr.gsu.edu/Hbase/Electronic/Dflipflop.html
The only thing that I can tell you for sure is that pushing the button pulls the D input low which (after the next rising clock edge) causes the Q output to go low, which causes its complement to go high, which lights up the LED. I have no idea what role the RESET line plays in this circuit.
By the way, I'm assuming that this is the switch debouncer that you posted in another thread about?