Without paging only 1 memory reference is required

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In x86 architecture, accessing memory with paging typically requires three memory references due to the multi-level paging process. The CPU first retrieves the page directory (PD) address from the control register (CR3), then uses the PD to find the page table (PT) address, and finally accesses the actual data from the page. Without paging, only one memory reference is needed because the instruction can directly access physical memory without any translation. However, if the translation lookaside buffer (TLB) contains the necessary virtual to physical address mapping, only two memory references are required. The discussion also notes that in systems with a flat real address space, all addresses are physical, eliminating the need for translation. Additionally, the use of segmentation can further complicate memory access patterns.
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"suppose there is an instruction to copy one register contents to another...
now,
without paging only 1 memory reference is required to fetch the instruction...but with paging..we need 3 memory reference (as page tables are to be accesed)..."

please explain why 3...?
 
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In x86, to access memory with paging, the CPU must get the address of the PD from cr3, then get the address of the PT from the PD, then get the address of the page from the PT, and then access the referenced data in that page.
 


whats PD,cr3 and PT...
without paging how come only 1 time memory to be referenced...?
 


prashantgolu said:
whats PD,cr3 and PT ... without paging how come only 1 time memory to be referenced...
Those are Intel X86 cpu components. How paging and segementation are used depends on CPU and the OS. Some environments would only need 2 memory references instead of 3. For the X86, if the TLB (translation look aside buffer) contains the virtual to physical address in it's memory, then only 2 memory references are needed. If the multi-level paging scheme is used and there isn't an entry in the TLB, then 3 memory references are needed, plus a 4 reference to update the TLB.

http://en.wikipedia.org/wiki/Page_table

http://en.wikipedia.org/wiki/Translation_lookaside_buffer

Complicating matter is that segmentation could also be used:
http://en.wikipedia.org/wiki/X86_memory_segmentation
http://en.wikipedia.org/wiki/Physical_Address_Extension

If a system has a flat real address space (no virtual memory), then all addresses or offsets are physical and can be used without translation.
 
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