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Would a four layer board be beneficial for me?

  1. Nov 7, 2011 #1
    I'm designing a circuit that consists of the following:

    1. AT Mega 128L
    2. 2 to 6 CPLDs
    3. SD Card Interface
    4. 100 to 200 MOSFETs
    5. Power circuitry

    I should add that I already have a 2-layer prototype of the board and it works well. However, the prototype does not have the MOSFETs and the SD Card Socket. The prototype is also on a smaller scale - it only has two CPLDs.

    The circuit is actually a automobile wiring harness checker. The harness can be upto 300 wires and is connected to the output of the CPLDs. The MOSFETs act as buffers for output of the CPLDs. I'm using a very small package to conserve space and the intent is to mount them on both sides of the board.

    In the current layout, 90% of the routing is on the top layer and the bottom layer is ground. However, as it's quite difficult to route everything on a single layer some tracks inevitable are routed through the bottom layer - which leads to a not-as-effective ground plane.

    With a large circuit, consisting of say 6 CPLDs, this will become more of an issue - and even more so because I'd like mount the MOSFETs on both sides of the board.

    So my question is, should I go for a 4-layer board which will allow me to have a dedicated power layer (3.3V) and a dedicated ground layer and two complete layers through which I can route the signals.

    My other question is - as I intend to include the voltage regulators on the board, do I simply source the power to the power layer using a via which connects to the output of the regulator? Or should I have multiple vias?

    My frequency of operation isn't very high (max. 4MHz) but I can even bring it down to 62.5kHz. Speed isn't important as the amount of data isn't large. However, signal integrity is very important.
  2. jcsd
  3. Nov 7, 2011 #2
    Yes, you save a lot of problems using 4 layer board with a solid ground plane. Now a days, price is not that big a difference between 2 and 4 layer and the last thing you want is to have to trouble shoot ground glitches caused by MOSFET turning on and off. Yes, those mosfet are something else, currrent surge is caused by charging and discharging the input capacitance. I would not even consider 2 layer boards with all these components, you are going to have a hack of a time laying out in two layer that has to contain power and ground.
  4. Nov 7, 2011 #3


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    I agree with yungman, and I'm very surprised that you've been able to do anything with just a 2-layer board so far.

    You definetly should use at least 4 layers for a dense digital board like this. The inner layers are the power and ground layers (with a little routing on them sometimes if it doesn't break up the planes too much), and the outer layers are signal routing with stitched ground pours in the open areas at the end of the layout.

    You will usually stitch the output of an SMT voltage regulator to the power plane with a few vias, but more important is to have SMT power supply decoupling cap at each power input pin for each of your other chips. The SMT decoupling caps should be on the same side of the PCB as the pin they connect to, placed as close to that pin as possible, with vias to power and ground very close to the cap. Good power and ground distribution and decoupling is important for signal integrity, and to help meet radiated EMI regulations (for products that you sell, not for in-house test fixtures).
  5. Nov 8, 2011 #4
    Thank you yungman and berkeman. Regarding current surges due to MOSFETs, I was actually planning on having a 1K resistance between the gate and the output pin of the CPLD. This could potentially limit the current when the gate capacitance is uncharged. I've seen this done before - what do you fellows think? Is it a good idea? I understand that it will probably limit the speed.

    And indeed, I have followed advice regarding decoupling and bulk capacitors to the book. I have a 0.1uF 0603 capacitor at every Power/Ground pin pair. I've put them as close as possible and on the same layer.

    I also have bulk capacitors, tantalum variety - around 47uF. And then a large power cap, where the power enters the board, about 1000uF - this one is electrolytic.

    One thing I'd like to ask further, as mentioned I plan on putting a 1K resistance between gate and the output pins. Should I also have a termination resistor at the input pins? The wiring harness can be quite long, about 10m, in length.

    Thanks again for the advice - there's no doubt I'd be going for a four-layer board now.

    EDIT: Some more questions. As this is my first four layer board, I'm sorta confused about vias. My PCB manufacturer does not do blind vias, so I'll have to do with through-hole.

    However, suppose I want to connect a surface mount decoupling capacitor to Vcc and GND. As the Vcc via will connect to the Vcc layer, how will it be isolated when it goes through the GND layer? Because otherwise, obviously, the via is short-circuiting the power and gnd planes.

    What about a through-hole capacitor? Will the pads be isolated from layers where the connection isn't supposed to go? If it matters, I'm using Altium.
    Last edited: Nov 8, 2011
  6. Nov 8, 2011 #5
    Any layer you want a via to go through, but not connect will have a gap as defined when you specify the specs for the fill zones.

    Im not familiar with the pcb package your using, but be mindful of how the vias are connected to the flood fills, most packages will automatically use thermal relief pads.
    If your expecting a device to be spitting more than 100mA (at a guess, cant remember the recommended value) make sure you have more than the one via in place.

    Also if you have any tracks running along the inner layers, be mindful that the current carrying limits of inner tracks is much smaller (as no outside enviroment to provide relief) theres loads of online calculators to figure out track sizes.

    Other thing to note, is your ground stiching, if you have a solid ground on one layer, if you intend to fill other layers with the same, try to not leave any area's with a large gaps between the stiching.

    Again I wouldnt worry about vias shorting, your pcb package should deal with them and leave a gap around non-connected layers. Just make sure you run the DRC checker, before gerbering.
  7. Nov 8, 2011 #6


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    Can you say a little more about this? Are you driving a signal out into the harness, and looking for it coming back?

    There are several options for terminations, and it would help to know what exactly the signal paths are, and if you are doing any slew-rate limiting of signals that are driven into the cable.
  8. Nov 8, 2011 #7
    Imagine there are two CPLDs, one is programmed as a Serial In Parallel Out shift register (this is the driving end) and another is a Parallel In Serial Out shift register. At the output of the driving end, I'll have MOSFETs acting as buffers. This has the advantage that I won't be sourcing current from the CPLD's pins. I need to be sourcing as much as 500mA, so a transistor is necessary.

    The other end of the harness is connected to the receiving end. My question is, should I have a termination resistor at this end?

    Serial In Parallel Out -> Buffers -> Harness -> (Termination?) -> Parallel In Serial Out

    The frequency of operation isn't very high (less than 10Khz, but I can even take it lower. As I said, speed isn't a factor), but the length of the harness can be upto 10m.

    The uC drives a test vector (just a walking 1) into the driving end and looks at the output. Because it knows beforehand what the output should be, the uC can determine if and where the fault is. I can provide more detail if you wish. Thanks for the response, I appreciate it.
  9. Nov 8, 2011 #8


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    Okay, that helps. And yes, you should either forward-terminate or back-terminate each driven line. But, it may be hard to decide what impedance to use -- are these twisted pairs in the harness, or just a bunch of single wires? Also, why do you need to source 500mA? Where does this current go?
  10. Nov 8, 2011 #9
    Okay, each wire will have a 4.7K pull up - the MOSFETs are used in Open Drain config. This pull up is located on the receiver side of the board. So, it's a bit like this:

    Output -> Buffer/MOSFET -> Harness -> Pull-up Resistor -> (termination?) -> Input

    Now here's the thing, for a single wire obviously the current isn't that much it's just 3.3V/4.7K = 0.7mA.

    However, this was assuming that all the wires in the harness are one-to-one. This is, of course, not always the case. Suppose there is a junction that has 50 wires. This junction will be connected to the driving end via 1 wire and the 50 wires will be connected on the receiving end. When the CPLD drives the walking 1 onto this wire, the transistor will need to source

    3.3/4.7K * 50 = 35mA.

    A simpler way to look at it is that the CPLD pin will be activating 50 pull up resistors in parallel. Even this isn't an issue - the real issue comes when there is a fault in the harness, the very thing the circuit needs to detect. Suppose this 50 contact junction is short circuited with another 50 wire junction. Suddenly, we don't have 50 pull ups in parallel, but a 100. Can you see how this gets out of hand? But remember, no matter what, only one output will be activated because the test vector is a walking 1.

    Sure, I could use a weaker pull up, but the current isn't an issue because I've already found a logic-level MOSFET that has a absolute max. I(DS) of 700mA, so I'm okay around here.

    The wires can be twisted, but they can also be single. They can even be shielded - it depends on what the customer requires and is out of our hands.

    Coming back to the current... the current doesn't go anywhere, it just runs through the harness and goes to ground through the MOSFET.

    Here's a rough outline of what I said:


    The resistor at the gate is connected to the output of the CPLD. The wires at the drain and onwards till the pull ups is symbolize the harness. The right hand side is connected to the input/receiving side.

    Does this make things more clear?
  11. Nov 14, 2011 #10
    About to design the receiving end of the board - any advice, berkeman regarding termination? Would appreciate any thoughts on it.
  12. Nov 14, 2011 #11


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    Oops, sorry for the delay.

    Since there is no characteristic impedance per se, you can't really benefit much from trying to come up with a "termination". Termination requires a reasonably well defined Zo.

    If you run the test slowly enough to allow for any ringing to die out, you should be okay.
  13. Nov 14, 2011 #12
    Not a problem. :) I appreciate the responses!

    Thanks. I had a hunch it would be that, but I wanted a more experienced engineer's opinion on the matter before I went ahead and designed the thing.
  14. Nov 15, 2011 #13
    Sorry to bump this thread again, but I had another question - should I be concerned about ESD damage? The wires can be quite long, about 10 meters. The output, as mentioned, has MOSFETs as buffers. However, the input side is completely naked with the exception of pull ups. Should I put in a ESD protection device like a TVS diode on this end? They're available in small packages and so routing them shouldn't be (too) much of a pain. Will need quite a few though!
  15. Nov 15, 2011 #14


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    Yes, you absolutely need to put ESD protection on any IO that connects to the outside world (where people can touch the wires, connectors, etc.).

    You could use TVS devices, but you should be able to just use diode clamps to the rails (power and ground).

    I googled Diode Clamp Array, and got lots of promising hits to check out:


  16. Nov 15, 2011 #15
    Thanks berkeman. Will check that out as well. I think TVS diodes also come in arrays, so that's promising as well.

    One more thing I'd like to ask - I asked this very question on another forum and was told I should add RF filtering as well. Would this be necessary?

    Incase the operational frequencies matter, I can run the system at a very slow speed and it's still not a factor. For instance, if I read out the output of 300 wires at 62.5kHz that means I'll be pushing my walking-one test vector every 4.8ms or every 208Hz. Testing the entire harness will take 1.4s + some extra time. 300 wires is an extreme case, a more typical is 150. If that's the case, then every 2.4ms (i.e. 416Hz) the test vector is pushed. Testing entire harness will take less than a second.

    Note, this isn't an issue because the operator of the machine is still the limiting factor as he/she has to plug and unplug the harness which takes more time than this.
  17. Nov 15, 2011 #16


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    I don't see a need for RF filtering in this application, unless you have an industrial welding robot at the next test station or something.
  18. Nov 15, 2011 #17
    Nope, just wire-crimpers but they're on the floor below and I don't think they cause much of a fuss. Wires at switched at 3.3V but we can take this upto 5V if needed.

    As an aside, in general, would a stronger pull up help us in this case? I mean, if I put in a 1K pull up than does this mean that signal will be less resistant to interference from RF?
  19. Nov 15, 2011 #18


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    NOt really. The pullups are at one end of the wire, so they don't help with RF induced voltages at the other end of the wire. Having pullups at both ends of the wire might help cut down on induced 60Hz noise a bit. You should be able to experiment a bit to see if there are any issues...
  20. Nov 15, 2011 #19
    Thank you, indeed the pull-ups are located at the input. In general, when does RF interference become an issue? Does it depend on the frequencies we're operating? I'm sure the length affects the things.

    I should add, we don't need to any certification for RF emission etc. because the units will never sold.
  21. Nov 15, 2011 #20


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    RF interference is a concern if it can affect the operation of the device. It also matters what environments the device will be in -- whether there area strong RF sources nearby putting out frequencies that can couple into the device or its wired connections.

    The classic example is a switching power supply in a device that can be near strong RF emitters. If the feedback control loop for the voltage regulation is not laid out well on the PCB, it can pick up the RF noise and rectify it, which can cause regulation to fail (poof!).

    Another classic example would be communication circuits using long twisted pair cables. If the cables can pick up RF noise that is near the resonant frequency of that length of cable, you can get significant common-mode RF voltages showing up on the ends of the cable. Good CM rejection by the transceivers is needed, and sometimes the cable terminations will include CM termination components.
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