
#1
Jan2812, 10:31 AM

P: 1

Hi guys, can someone explain to me what is going on. I have no clue of what does the question want. I am unable to copy down the diagram. But each module is connected to an AND gate. Such that a AND b, b AND c, a AND c and I would have to tell which is the correct output. 



#2
Feb212, 01:58 AM

P: 972

With triple modular redundancy they assume:
zero errors happen most of the time, one error happens rarely and two or more errors happen almost never, you sometimes or often assume this never happens. So if you look at your outputs I think you should be trying to look at each column. If you do that and you use the assumptions above then what do you get? Different issue, are you sure those are AND gates and not XOR or XNOR gates? You might want to think why I would ask a question like that. 


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