2-switch forward converter -- transformer reset question

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The discussion focuses on the operation of a 2-switch forward converter with synchronous rectifiers, specifically addressing transformer reset during the off state. The primary voltage can reach 330V, necessitating careful timing of the synchronous rectifiers due to the non-instantaneous turn on/off characteristics of the primary FETs at a switching frequency of 200kHz. The need for volt*second balance during both the D and 1-D states is emphasized to ensure proper transformer reset. A PSPICE simulation indicates a lack of volt*second balance, suggesting that synchronous rectifier overlap must occur during the dead time of the 1-D state.

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Switching power converter question (FYI, this is a 2-switch forward with synchronous rectifiers on the secondary). Switching at 200kHz.

The transformer stores & transfers energy during the on state (the "D" state), and then must be reset during the off state ("1-D" state).

The primary voltage of the converter can be as high as 330V, so the primary FETs - even ones with a relatively low COSS - will, at this frequency, have a non-negligible slope to their VDS turnon & turnoff; thus the timing of the synchronous rectifiers must take into account the reality of the lack of near-instantaneous turn on/off of the primary FETs.

Recall that the output inductor is carrying AC currents, and if the DC level of the output current is low enough, some of the AC current in the inductor will be <0A ("second quadrant"). The synch FETs have to have a (small) time during the 1-D state when they are both on, in order to provide a path for these possible second quadrant currents (otherwise the output inductor current would have no where to go, and the switch node would then see a large, uncontrolled voltage spike). But this also has the effect of shorting the secondary side of the transformer, which isn't necessarily an issue during the 1-D state.

Now, the way you guarantee that the transformer resets is to make sure there are an equal amount of volt*seconds applied to the transformer in both the D and 1-D states.

So, here's the question: If the transformer is not completely reset before the small time during the 1-D state when the synchronous FETs simultaneously conduct, how can I convince myself that I am resetting the transformer?

From one point of view, you'd think that the short (well, two RDSon in series) on the secondary would reset the transformer for sure... but given that the transformer is inductive itself, its current can't instantaneously change from it's pre-short current to the short current... yet both of these currents are flowing in the same direction, so I think the polarity of the transformer secondary can't change during this event.

Any ideas?

Thanks. :)
 
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Hmmm... a PSPICE run indicates I do not have volt*second balance in this case. This makes me think that the overlap in synchronous rectifier on times must occur during the "dead time" of the 1-D state, between the time when the transformer resets and the 1-D state ends.
 

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