Admittance Matrix: Building Complex Discrete Laplacian Operators

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Hi,

I'm a mathematician looking for someone who can find analogies between what I'm going to explain (part of my research) and what is known in the electrical network theory. Everyone probably knows that for an AC network is possible to build an Admittance Matrix Y, such that:

Y V = I,

where V and I are vectors containing the potentials and the currents of each member of the network. This set of linear equations can be simply obtained by writing the Kirchhoff's laws of the network, and grouping them together in the above notation. Now, the same is possible for steady circuits, using the Conductance Matrix G:

G V = I.

Less known is that this latter equation can be obtained also from the Discrete Laplace Operator of the network. From mathematics, the continuous Laplace operator ∆ acting on real-valued functions can be written as ∆=d*d, where d* is the adjoint operator of d. The important thing to understand is that d can be defined for discrete and continuous functions.

Interestingly, d can be built to be simply the adjacency matrix of the network, while d* contains informations about conductances. More precisely, d* requires the construction of a metric over the network, which will be defined by Ohm's law. Note that the canonical mathematical construction of discrete d and d* (gradient and divergence) satisfies automatically also Kirchhoff's laws.

Now my question is: does this construction sounds familiar of completely enigmatic? Do you know how to extend it to AC networks to get a sort of "Complex Discrete Laplacian Operator"? If someone is willing to join the discussion, I can be more specific regarding the construction of ∆.
 
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I think that post was from 2009. Not sure if the author is still around... :)
G.V=I is just KCL and is at the center of the spice algorithm so that's pretty familiar.
http://www3.imperial.ac.uk/pls/portallive/docs/1/7292571.PDF
Honestly, I didn't really follow the argument for what one gains by using the Laplacian Operator. It seems like we know the adjacency because we have the schematic (and we were able to create G) but it's very likely I'm missing something.
 
Actually, now that I’ve thought about it testing for adjacencies could be very useful in security applications. If one thought of the chip as an n-port black box (so I can’t just look at the schematic) then knowing adjacency could be very useful. Say I could not get at node Va but I could get at an adjacent node Vb. Then I might be able to bit flip at Va by injecting a current into Vb. Or something like that. :)