Calculating Midband Gain for NPN BJT: Are My Results Accurate?

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The discussion revolves around calculating the midband gain for a 2N3904 NPN BJT, with the user reporting a gain of 0.748 and questioning the accuracy of their calculations. They highlight a significant source impedance of 100kΩ, which is causing attenuation of the output signal. The conversation emphasizes that the emitter resistor (RE) cannot be fully bypassed with a pure capacitor, and the user is advised to reconsider their calculations due to the heavy input attenuation. They also inquire about measuring input and output impedance, seeking clarification on the correct methods for obtaining these values. Overall, the user is trying to reconcile their theoretical understanding with practical lab results.
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Homework Statement


I just have to calculate midband gain for a typical NPN BJT. The transistor model is a 2N3904
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Have I calculated something wrong?? My gain is 0.748
 
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RE is not bypassed? So what is its value?

100kΩ is a very high source impedance! You are losing most of your gain there.
 
RE is bypassed, as all capacitors are shorted (internal are open). Source impedance is verified as 100k ohms
 
r19ecua said:
RE is bypassed, as all capacitors are shorted (internal are open).
Okay, but CE = 0 is not the way to express RE being fully bypassed!

Source impedance is verified as 100k ohms
So your have a large attenuator in front of your amplifier stage. Perhaps you should exclude RS from your calculations, so as to present a truer picture?
 
I can't change RS because that's the lab problem and I have no idea why I set all caps to zero, but I understand that CE = 0 is the incorrect way of expressing a short circuit. I calculated mid-band gain however, and my notes read a gain of about 34dB. Where as my calculations show a dB of 2.4 (after 20*log (0.748). So would it be safe to conclude that my output voltage is attenuating and that my value calculated in class is incorrect?
 
This circuit will not work right. You can't bypass the emitter resistor with a pure capacitor. The gain will climb with frequency until the transistor becomes beta-limited. A poor design.

Eliminate CE and you have a hi-pass circuit with the upper frequency rolloff determined by transistor specs only.
 
It would be worth going over your calculations, checking carefully. For example, that second last line which you equate to 0.748, does that line look right to you?

Whatever gain your transistor stage contributes, it will be largely undone by the heavy attenuation at the input, the attenuator RS and RB'. So I'm not surprised that overall you may appear to have a gain of less than -1.
 
Everyone, I understand what you are all trying to say. With this circuit, gain is less than 1, which means my input resistance is attenuating the output signal by a factor of 0.748. The circuit is not amplifying anything. This was a lab practice problem, I just wanted to know where my calculations were off.

Now, my peak to peak input is 12.6V and my output, (where it's steady BW) is 8.8V. So if everything up to this point is correct, in order to find my -3dB points on the oscilloscope is to multiply the 8.8V by 0.707V. Then, in order to find the frequencies that operate at 6.2V
(8.8 * 0.707V), I need to change the cursors to read a peak-to-peak voltage of 6.2V and start sweeping frequencies (turning knob on function generator).

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Based off of this picture, my calculations are slightly off, but the concept is correct. Please let me know if what I've said is totally wrong! If not, my last inquiry would be this:
How do you measure input and output impedance? Do I just place my DMM and measure the resistance? Am I suppose to break the circuit? I know how to calculate it (haven't yet), but by finding Z-thevenin, this value should net me Zin. I believe Zout is just the RL'... Please tell me if I"m incorrect
 
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If you measure the voltage on both sides of Rs you can calculate your Zin, so measure the signal at the base using a probe of sufficiently high impedance so it doesn't affect the conditions.
 
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