# Circuit design

I am given 4 chips: 2-input NAND, 2-input NOR, NOT and 3-input NAND gate chips to implement following functions (*- AND, + OR, '-NOT):
F(X, Y, Z) = X*(Y' + Z) + X'*Y
F'(X, Y, Z) and a dual of F... all simultaneously.
Input are DIP switches.
Dual i have not figured out yet, complement should be easy: just run the output of F through the inverter.

But i have a concern: the way i designed F is that I run A LOT of stuff through the inverter, and my breadboard is all in wires. And so far i have not used 3-input NAND, maybe it would be used with dual (since i have to change operators). Is there an easier way (that i don't see) to implement F?

I was trying to simplify the expression and I would get
X(xor)Y + Z*X, but i am not supposed to use XOR chip.
Any help is very much appreciated.

Related Electrical Engineering News on Phys.org
Your wording is not clear. Can you state what you are after more clearly?

KM

Kenneth Mann said:
Your wording is not clear. Can you state what you are after more clearly?
yeah, sure, attempt #2:
* stands for logical AND, + for OR, ' for NOT (just explaining notation i use)

so, i need to implement simultaneously these logical expressions (F, F', dual of F - shown below) on my breadboard using chips: NAND (2-input), NAND (3-input), NOR (2-input) and hex inverter (NOT gate or 74HC04).

F = X*(Y' + Z) + X'*Y

so, the way i implemented F function so far looks very crowded on my breadboard. For example: for X*(Y' + Z) i had to run a wire (Y) through inverter then connect it and wire for Z to the NOR and then connect output from NOR back to the inverter, since i need OR and not NOR...
so I am wondering if i am missing some logic simplification, i have tried different things but cannot simplify it. XOR is not allowed.
If something is still not clear, please...tell me again, English is my 2-nd language after all :)

Last edited:
How many "Gates" are you given? My guess is the following:
four- 2 input AND (on one chip)
four- 2 input NOR
three- 3 input NAND
six- INVERTERS
Is this correct?

First, I'd suggest defining the exact terms of F'. Then put F and F' so that they both have the same input terms (one will be inverted and have to be re-inverted at the end). Finally, combine the like terms and put them into two (3 input) NANDS to get the two functions (one will be inverted).

Erm...sorry, you're right: each chip has several gates.
Thank you for clarification there Each input-output pair of pins can be used only once, right?
so do you forsee usage of the hex inverter A LOT, like it seems to me?

Generally, inputs can be used only once, but outputs can be fanned out all over the place. Offhand, I see a most likely use for four inverters, one for each of the inputs, and one for one of the gate outputs.

KM

Thing is ... that i need to implement 3(!) functions on one breadboard at the same time: that function F, it's complement F' (easy...just hook it up to the inverter and get the output) and it's dual, which i think should be something like reversing operators from AND to OR and from OR to AND, so from F i would get a F(dual): X+(Y'*Z) * X' + Y, not sure about parenthesis though...and not sure that i would have enough space on the breadboard.

Question: What do you mean by 3(!) functions? The only things that I see that you need, are F and F(dual).

Do the following:
1) Put F into its Simple Sum Of Products form, ie. - - - (A*B)+(C*D)+(E*G).
2) Get F(dual) from F. It will be in a Simple Product of Sums SPOS) form, ie (A + B)*(C + D)*(E + G), to correspond to F.
3) Find F(dual)', which will then also be in SSOP form.
4) Use these values to wire the gates. Remember, that SSOP is implemented by simply taking the items that are now being And'ed (the terms within the parentheses) into NAND's. These outputs are then Or'ed by taking the proper outputs (inverted) from the NANDs, and sending them to additional NANDs. In other words, we get the ANDs to ORs functions, by using NANDs to NANDs.
5) Finally, the F(dual)' has to be inverted (put through an inverter, to get F(dual).

Note: I hate using such representations as N' instead of {N with a 'bar' over it}, but I understand that the limitations of Microsoft and HTML force it. It makes manipulating Logic equations messy.

KM

Last edited:
thanks for more explanation and hint on SSOP, but question:
for a function A*B + C*D, wouldn't the dual be (A + B) *(C + D) or does the negation also apply?
thanks much.
EDIT: what i meant by 3 functions was: F, F' and dual of F.

Last edited:
EvLer said:
thanks for more explanation and hint on SSOP, but question:
for a function A*B + C*D, wouldn't the dual be (A + B) *(C + D) or does the negation also apply?
thanks much.
EDIT: what i meant by 3 functions was: F, F' and dual of F.
You are correct; the dual is not negated; that isn't done until the actual negation is taken.
So if you have: F = (A + B)*(C + D)*(E + G)
The Dual is: F(dual) = (A * B) + (C * D) + (E * G)
And: F(dual)' = (A' + B') * (C' + D') * (E' + G')

The reason for the question about the three functions is: Does the solution call for giving an output for both the dual and its negation or just the dual?
(The difference is only the matter of an inverter on the output.

KM