Creating a decoder (Graycode to Binary) using 4 nands

[rugerts]

Homework Statement

Shown below as a picture.

Relevant Equations

No equations. There's a data sheet that I've provided as a link below.

These are the two questions.Here's a datasheet for the demux I've been using: https://ecee.colorado.edu/~mcclurel/sn74ls138rev5.pdf

Here's my work:

If you need to see how I got these sum functions, here's the work for that:

Now, if you look at the datasheet for the demux (linked above), you'll see its logic diagram. I'm confused as to how I can apply this to my situation to answer the second question about using 4 nand's when the logic diagram shown in the sheet uses 8 nands.

 

[Anachronist]

I'm hazarding a guess here, but I think that if you write out the logical expressions using 8 not-ands, you may be able to combine common terms to reduce it to 4 not-ands.

 

[collinsmark]

I'm not sure I understand the problem correctly because you haven't indicated what "Experiment 3.2.2" is. But I'm assuming that you are supposed to ultimately generate the original binary bits (not Gray code) from the outputs of the decoder/demux.

You need to use the 7 different BOUTL0_L to BOUTL7_L as inputs to your NAND gates, not the G0, G1, and G2 signals.

Start by filling the remaining elements of the table. (In the table below, the BOUTLx_L are denoted by $\overline{O_x}$ to save space.)

$$\begin{array}{|c | c | c | c | c | c | c | c | c | c | c | c | c | c |} \hline G_2 & G_1 & G_0 & \overline{O_7} & \overline{O_6} & \overline{O_5} & \overline{O_4} & \overline{O_3} & \overline{O_2} & \overline{O_1} & \overline{O_0} & B_2 & B_1 & B_0 \\ \hline 0 & 0 & 0 \\ \hline 0 & 0 & 1 \\ \hline 0 & 1 & 1 \\ \hline 0 & 1 & 0 \\ \hline 1 & 1 & 0 \\ \hline 1 & 1 & 1 \\ \hline 1 & 0 & 1 \\ \hline 1 & 0 & 0 \\ \hline \end{array}$$

Then use the appropriate BOUTLx_L signals (denoted as $\overline{O_x}$ here for short) as the inputs to your NAND gates.

Hint: No Karnaugh maps are necessary. If you find yourself making a K-map, you're making it too complicated. If done correctly, the answer is easy.

Another hint: Don't forget DeMorgan's theorem. A NAND gate not only functions as an AND gate with inverted output, it also functions as an OR gate with inverted inputs.

Also, to be clear, you need a total of 3 NAND gates (not 4), where each gate has 4 inputs.