Deciding Miller Index when building a transistor?

AI Thread Summary
Choosing wafers with the same Miller indices is crucial for optimal lattice matching, as different lattice structures can significantly affect transistor properties. The interaction between wafers is important when integrating multiple types, such as n-type and p-type, to form junctions like NPN. The proposed method involves cutting small squares from n-type and p-type wafers, attaching them to create a junction, and then processing them to form an oxide layer and etch for source and drain. Concerns are raised about the feasibility of this approach and whether it has been successfully implemented in practice. The discussion highlights the complexities of wafer integration in transistor design.
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In obtaining the materials to build a transistor, should one choose wafers of the same Miller indexes? Will the lattice structure affect the interaction between two wafers?
 
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What do you mean with interaction between two wafers? (How) do you want to use multiple wafers for a single transistor?

Different lattice structures will (in general) lead to different transistor properties.
 
mfb said:
What do you mean with interaction between two wafers? (How) do you want to use multiple wafers for a single transistor?

Different lattice structures will (in general) lead to different transistor properties.

The plan is to attach n-type wafers on the ends of a p-type. How would you go about doing this? How will the lattice structure effect the properties?
 
Are we talking about the same thing? Those wafers can have billions of transistors on them, but putting them mechanically together does not give a transistor.
 
mfb said:
Are we talking about the same thing? Those wafers can have billions of transistors on them, but putting them mechanically together does not give a transistor.
I would cut 2 small squares from the n-type wafer and one from the p-type, I would then attach them to form an NPN junction, after that I would place the apparatus in a kiln to form an oxide layer on the lattice, then etch out sections for the source and drain. It would look something like this.
 

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I would be surprised if that works. Who came up with that idea and are there working examples?
 
Maybe its like a transistorized relay?
 
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