- This isn't a homework problem but it's a question I had in mind when I was reading about Differential Amplifiers with Active Loads in the book "Design of Analog CMOS Integrated Circuits" by Behzad Razavi.
The highlighted part is what I don't understand. Due to the gate voltage increase in M1, the current in the left branch should increase. That makes sense to me. However, he then says that the voltage at node F (in other words the drain of M1) decreases? How?
Look at this plot:
As current in the NMOS device increases, the drain-source voltage Vds also increases. Thus shouldn't voltage at node F (drain of M1) also increase? Why has he said it decreases?