Differential Amplifier with an Active Load

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  • Thread starter CoolDude420
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Homework Statement:

This isn't a homework problem but it's a question I had in mind when I was reading about Differential Amplifiers with Active Loads in the book "Design of Analog CMOS Integrated Circuits" by Behzad Razavi.

Relevant Equations:

N/A
5dbe799e2f.png

5097af040e.png


The highlighted part is what I don't understand. Due to the gate voltage increase in M1, the current in the left branch should increase. That makes sense to me. However, he then says that the voltage at node F (in other words the drain of M1) decreases? How?

Look at this plot:
42d9a9d2d4.png


As current in the NMOS device increases, the drain-source voltage Vds also increases. Thus shouldn't voltage at node F (drain of M1) also increase? Why has he said it decreases?
 

Answers and Replies

  • #2
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As current in the NMOS device increases, the drain-source voltage Vds also increases. Thus shouldn't voltage at node F (drain of M1) also increase? Why has he said it decreases?
You need M3 to have a negative resistance to increase voltage at point F after application of increased voltage at gate of M1. As long as differential resistance of M3 is positive (always for diode-connected MOSFET), any increase of M1 current will result in drop of voltage at point F.
 
  • #3
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You need M3 to have a negative resistance to increase voltage at point F after application of increased voltage at gate of M1. As long as differential resistance of M3 is positive (always for diode-connected MOSFET), any increase of M1 current will result in drop of voltage at point F.
I don't understand. If you just look at M1. The gate-source voltage has increased, the current has increased. How is it possible that the drain voltage decreases? Surely, that pushes towards the linear/triode region?
 
  • #4
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I don't understand. If you just look at M1. The gate-source voltage has increased, the current has increased. How is it possible that the drain voltage decreases? Surely, that pushes towards the linear/triode region?
It is not very meaningful to look on M1 alone to estimate its terminal voltages because it not connected to any voltage node directly. All connections are through current sources. For manual voltage estimation, use devices connected to voltage nodes (M3 in this case).
 
  • #5
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It is not very meaningful to look on M1 alone to estimate its terminal voltages because it not connected to any voltage node directly. All connections are through current sources. For manual voltage estimation, use devices connected to voltage nodes (M3 in this case).
I see.
So in the I/V characteristic plot, the slope increase (increase in Id for increase in Vds) in the saturation region is just to show the effect of the channel-length modulation right? And I shouldn't be using that here?
 
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  • #6
Joshy
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The way that would feel less complicated for me is to think of that top M3 as a resistor above M1. If you increase the current of M1 then the voltage across M3 increases

$$V_{M3}=I_{D,M1} \times R_{M1}$$
$$V_{F}=VDD-V_{M3}=VDD-(I_{D,M1} \times R_{M1})$$

I really like the logic that trurle used. If VF increases and ID increases, then RM1 would have to be negative.
 
  • #7
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The way that would feel less complicated for me is to think of that top M3 as a resistor above M1. If you increase the current of M1 then the voltage across M3 increases

$$V_{M3}=I_{D,M1} \times R_{M1}$$
$$V_{F}=VDD-V_{M3}=VDD-(I_{D,M1} \times R_{M1})$$

I really like the logic that trurle used. If VF increases and ID increases, then RM1 would have to be negative.
This is where my confusion usually comes in. A lot of people tend to argue that you can't think of M3 just as a resistor and I keep finding myself going back and forth between following I/V curves and these "resistor" explanations.

I understand that M3 will appear as a resistor to small-signal but in large-signal analysis it can't be a resistor if it's saturation.
 
  • #8
Joshy
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I thought this was small-signal? My mistake.

Let's stipulate something odd for a thought: VF increases when the VG,M1 increases.

Let's think about that. The result of VG,M1 increasing is iD,M1 increases too, right? Would you agree that iD,M1 and iS,M3 is the same too? iS,M3 and iD,M3 are the same, right? If VF is increasing, then somehow it would eventually go to or above VDD, right?

This would actually be very amazing. I would imagine a lot of engineers would be thrilled to find a PMOS (or any MOSFET really) that has an ron that is negative or even just zero would be good enough. I don't recall large signal very well and might be babbling here, but even when the small signal becomes large enough to reach those non-linear triode region its IV characteristics will still have a slope that's non-negative just acts like a smaller resistor.
 
Last edited:
  • #9
rude man
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Homework Statement:: This isn't a homework problem but it's a question I had in mind when I was reading about Differential Amplifiers with Active Loads in the book "Design of Analog CMOS Integrated Circuits" by Behzad Razavi.
Relevant Equations:: N/A

View attachment 255198
View attachment 255199

The highlighted part is what I don't understand. Due to the gate voltage increase in M1, the current in the left branch should increase. That makes sense to me. However, he then says that the voltage at node F (in other words the drain of M1) decreases? How?

Look at this plot:
View attachment 255200

As current in the NMOS device increases, the drain-source voltage Vds also increases. Thus shouldn't voltage at node F (drain of M1) also increase? Why has he said it decreases?
Use the equation for a MOSFET biased in the linear mode. Recognize that ## V_{GS} = V_{DS}. ## Solve for ## V_{GS} as a function of current I.
 

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