# Differential Amplifier with an Active Load

• Engineering
• CoolDude420
In summary: Substitute this into ## V_{GS} = \sqrt{2I/\mu C_{OX}}. ## Solve for the current I as a function of ## V_{DS}. ## As Vds increases, I increases, so Vgs increases, so Vds increases.
CoolDude420
Homework Statement
This isn't a homework problem but it's a question I had in mind when I was reading about Differential Amplifiers with Active Loads in the book "Design of Analog CMOS Integrated Circuits" by Behzad Razavi.
Relevant Equations
N/A

The highlighted part is what I don't understand. Due to the gate voltage increase in M1, the current in the left branch should increase. That makes sense to me. However, he then says that the voltage at node F (in other words the drain of M1) decreases? How?

Look at this plot:

As current in the NMOS device increases, the drain-source voltage Vds also increases. Thus shouldn't voltage at node F (drain of M1) also increase? Why has he said it decreases?

CoolDude420 said:
As current in the NMOS device increases, the drain-source voltage Vds also increases. Thus shouldn't voltage at node F (drain of M1) also increase? Why has he said it decreases?
You need M3 to have a negative resistance to increase voltage at point F after application of increased voltage at gate of M1. As long as differential resistance of M3 is positive (always for diode-connected MOSFET), any increase of M1 current will result in drop of voltage at point F.

trurle said:
You need M3 to have a negative resistance to increase voltage at point F after application of increased voltage at gate of M1. As long as differential resistance of M3 is positive (always for diode-connected MOSFET), any increase of M1 current will result in drop of voltage at point F.

I don't understand. If you just look at M1. The gate-source voltage has increased, the current has increased. How is it possible that the drain voltage decreases? Surely, that pushes towards the linear/triode region?

CoolDude420 said:
I don't understand. If you just look at M1. The gate-source voltage has increased, the current has increased. How is it possible that the drain voltage decreases? Surely, that pushes towards the linear/triode region?
It is not very meaningful to look on M1 alone to estimate its terminal voltages because it not connected to any voltage node directly. All connections are through current sources. For manual voltage estimation, use devices connected to voltage nodes (M3 in this case).

trurle said:
It is not very meaningful to look on M1 alone to estimate its terminal voltages because it not connected to any voltage node directly. All connections are through current sources. For manual voltage estimation, use devices connected to voltage nodes (M3 in this case).

I see.
So in the I/V characteristic plot, the slope increase (increase in Id for increase in Vds) in the saturation region is just to show the effect of the channel-length modulation right? And I shouldn't be using that here?

trurle
The way that would feel less complicated for me is to think of that top M3 as a resistor above M1. If you increase the current of M1 then the voltage across M3 increases

$$V_{M3}=I_{D,M1} \times R_{M1}$$
$$V_{F}=VDD-V_{M3}=VDD-(I_{D,M1} \times R_{M1})$$

I really like the logic that trurle used. If VF increases and ID increases, then RM1 would have to be negative.

Joshy said:
The way that would feel less complicated for me is to think of that top M3 as a resistor above M1. If you increase the current of M1 then the voltage across M3 increases

$$V_{M3}=I_{D,M1} \times R_{M1}$$
$$V_{F}=VDD-V_{M3}=VDD-(I_{D,M1} \times R_{M1})$$

I really like the logic that trurle used. If VF increases and ID increases, then RM1 would have to be negative.

This is where my confusion usually comes in. A lot of people tend to argue that you can't think of M3 just as a resistor and I keep finding myself going back and forth between following I/V curves and these "resistor" explanations.

I understand that M3 will appear as a resistor to small-signal but in large-signal analysis it can't be a resistor if it's saturation.

I thought this was small-signal? My mistake.

Let's stipulate something odd for a thought: VF increases when the VG,M1 increases.

Let's think about that. The result of VG,M1 increasing is iD,M1 increases too, right? Would you agree that iD,M1 and iS,M3 is the same too? iS,M3 and iD,M3 are the same, right? If VF is increasing, then somehow it would eventually go to or above VDD, right?

This would actually be very amazing. I would imagine a lot of engineers would be thrilled to find a PMOS (or any MOSFET really) that has an ron that is negative or even just zero would be good enough. I don't recall large signal very well and might be babbling here, but even when the small signal becomes large enough to reach those non-linear triode region its IV characteristics will still have a slope that's non-negative just acts like a smaller resistor.

Last edited:
CoolDude420 said:
Homework Statement:: This isn't a homework problem but it's a question I had in mind when I was reading about Differential Amplifiers with Active Loads in the book "Design of Analog CMOS Integrated Circuits" by Behzad Razavi.
Relevant Equations:: N/A

View attachment 255198
View attachment 255199

The highlighted part is what I don't understand. Due to the gate voltage increase in M1, the current in the left branch should increase. That makes sense to me. However, he then says that the voltage at node F (in other words the drain of M1) decreases? How?

Look at this plot:
View attachment 255200

As current in the NMOS device increases, the drain-source voltage Vds also increases. Thus shouldn't voltage at node F (drain of M1) also increase? Why has he said it decreases?
Use the equation for a MOSFET biased in the linear mode. Recognize that ## V_{GS} = V_{DS}. ## Solve for ## V_{GS} as a function of current I.

## 1. What is a differential amplifier with an active load?

A differential amplifier with an active load is a type of electronic amplifier that amplifies the difference between two input signals. It uses an active load, such as a transistor, to provide a high gain and improve the overall performance of the amplifier.

## 2. How does a differential amplifier with an active load work?

A differential amplifier with an active load works by taking two input signals and amplifying the difference between them. The active load provides a high gain and helps to reduce the effects of variations in the input signals. The amplified output is then fed back to the inputs to further improve the performance of the amplifier.

## 3. What are the advantages of using a differential amplifier with an active load?

There are several advantages to using a differential amplifier with an active load. These include high gain, improved linearity, and reduced sensitivity to variations in the input signals. It also provides a high input impedance, low output impedance, and good noise performance.

## 4. What are the applications of a differential amplifier with an active load?

A differential amplifier with an active load is commonly used in applications that require high precision and accuracy, such as in instrumentation and control systems. It is also used in audio amplifiers, communication systems, and data acquisition systems.

## 5. How is a differential amplifier with an active load different from a regular differential amplifier?

A differential amplifier with an active load differs from a regular differential amplifier in that it uses an active load, such as a transistor, to provide a high gain and improve the overall performance of the amplifier. This allows for better linearity, reduced sensitivity to variations in the input signals, and improved noise performance.

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