Distributing a clock signal using a clock fanout buffer

[Tom48]

hi,

im trying to distribute a clock signal using a clock fanout buffer.
I have an oscillator and i need to get its clock signal to 4 other devices.
My first idea was to supply the clock signal of the oscillator to a clock buffer.

I have chosen this clock buffer:
http://www.onsemi.com/pub_link/Collateral/SB3N551-D.PDF

Could i drive it with the following oscillator?
http://www.taitien.com/wp-content/uploads/2015/12/XO-0084_TW_TYPE_TCXO.pdf

Would this work?
Can it work?
Or what kind of problems could i run into?
What exactly do i have to keep in mind when choosing a clock buffer? (except for what frequency it can handle of course).Thank you a lot in advance! :)

 

[Baluncore]

Is your clock signal a rectangular pulse, a clipped sinewave or a sinewave ?
What frequency do you need ?
Why do you need a dedicated clock distributor ?

 

[Tom48]

Hi Baluncore,

thank you for your answer.
The oscillator should provide a clipped sinewave output signal.
Is the clock buffer i chose not capable of handling clipped sinewaves?

I need 28.8MHz.

I would like to synchronize multiple SDR-Sticks (4 SDRs at whole).
Each SDR-Stick is clocked with a 28.8MHz TCXO.
I want to remove the TCXO from each SDR-Stick and use one of these TCXOs to clock all 4 of the SDR-Sticks simultaneously.
Thats the reason i need the clock buffer (at least i think so ;))

Thank you!

 

[berkeman]

What is your termination scheme? How long are the traces from the buffers to the SDRs?

 

[Tom48]

What is your termination scheme? How long are the traces from the buffers to the SDRs?

Hi berkman,
thanks for your reply!
I drive the clock buffer i posted above directly with the TCXO.
Do i have to calculate the line for a 50Ohm environment? (what exactly do you mean by 'termination scheme'?)
Because right now the oscillator seems to work but the clock buffer shows no reaction at the outputs.
Traces are about 50cm each. (i used a 33ohm termination series resistor for each output-trace)

Thanks :)

 

[lewando]

What are you doing with the OE pin of the clock buffer?

 

[Tom48]

Hi lewando,

thanks for your reply!
I left the OE pin of the buffer open. Is that the fault?
In the datasheet of the buffer i posted it says (on page 2):

OE = Output Enable for the clock outputs. Outputs are enabled when HIGH or when left open; OE pin has internal pull−up resistor. Three−states outputs when LOW.

I checked the voltage at that pin when connected to a power supply and it said 3.3V (due to the pullup resistors).
So that should be correct or did i make a mistake?

thanks!

 

[lewando]

That is okay--just trying to eliminate the usual suspects.

the oscillator seems to work but the clock buffer shows no reaction at the outputs

Have you observed the clock signal directly at pin 1 of the [buffer] IC?

 

[Tom48]

No i did not yet.
I need an oscilloscope to do that and i need to wait some more days until i get access to one.
Until then i wanted to ask regarding the clock buffer if i made an obvious mistake.

A TCXO normally provides a clipped sine wave output signal.
Is this buffer ok with that? As the datasheet says the buffer accepts only (LV)CMOS/(LV)TTL as input signals.

So can this buffer still work with an input signal that is a clipped sine wave?

thank you for the help so far! :)

 

[lewando]

Short answer: that buffer will not work directly with that TCXO. If you can get a TCXO with a CMOS output it would work. The family of TCXO you picked has this option (available in same footprint).

The issue is the "high" voltage level coming out of the TCXO is probably going to be too low to trigger the CMOS input "high" level (if you are operating at 3.3V).

 

[Tom48]

i see...
In case i don't have the option to pick another oscillator, what other options do i have?
Are there clock buffers available that would work with such low input clock signals?
How about this one?
http://www.idt.com/document/621-datasheet

Would a level shifter like this one maybe be another option?
level shifter: http://www.ti.com/lit/ds/symlink/sn74lvc2t45.pdf

thanks a lot for the help so far!

 

[berkeman]

Do i have to calculate the line for a 50Ohm environment?

Not necessarily.

(what exactly do you mean by 'termination scheme'?)

Depending on the length of the transmission line (TL), you may need to terminate it to avoid reflections and the resulting ripple and false triggering.

Traces are about 50cm each.

Holy cow! Why so long?

(i used a 33ohm termination series resistor for each output-trace)

That may be a good value. How did you decide on that value of series (back) termination?

I left the OE pin of the buffer open. Is that the fault?

Do not leave CMOS inputs open -- that is bad for several reasons.

 

[Baluncore]

My suspicion is that a SDR will have a digital synthesiser driven by the TCXO. The nature of that synthesiser and the way it starts will probably destroy any phase information of the TCXO. I expect that you will benefit from locking the distributed frequency, and that synchronising the phase of the first local oscillators will not be possible by locking the phase of the distributed common reference oscillators.

We could better assess the synchronisation possibilities if we knew which chipset the SDR uses ?

The impedance matching of a TCXO to a synthesiser on a PCB will be quite different to distributing clock signals over coaxial cables. As a distribution amplifier I would use a single power amplifier with a gain of two. Then I would use 50 ohm series resistors to fan that one signal into several 50 ohm cables, all of the same length. The end of the cables would be terminated with 50 ohm to ground. The reference oscillator inputs to the SDR may not be 50 ohm, it is more likely to be nearer 300 ohm. You will therefore need to use a parallel termination resistor of about 60 ohms to ground at the mixer LO inputs. That will match both ends of all transmission lines.

If you are wanting to lock the phase of the first LOs and RF down converters then you may need to distribute the first LO rather than the reference oscillator. A better alternative might then be to phase lock all but one of the first LOs to one LO as the reference. That would keep all the signals intact on the PCBs. Sniffing the LOs, phase detecting them and feeding back the voltage control signal will lock the frequency and phase of all LOs.

How many LOs are there in the chipset and what level of frequency and phase synchronisation is required ?

 

[lewando]

[response to post #11]:

If you want to use the IDT part, it could be made to work due to its low voltage operating range (1.2V to 1.8V), but you would need to AC couple the TCXO output to the input of this device and bias the clock (on the IDT side) at VCC/2. Also with this part, you would need to consider level shifting downstream.

The TI level shifter should work, using similar AC coupling and biasing. Since this part is not explicitly designed for clock distribution, its not clear from datasheet how much jitter, if any, this part would add (if you have a minimum jitter requirement).

And here's yet another option:
http://www.pletronics.com/ple/articles/view/401

 

[Tom48]

ok, thanks so much for all the information so far!

A bit more about the project.
This is the SDR i use:
http://www.nooelec.com/store/sdr/sdr-receivers/nesdr-smart.html

I have 4 of this SDR-devices and i would like to clock them all with the same clock signal in order to synchronize them.
So i want to remove the TCXO from all 4 devices and use one of the removed TCXOs to clock all 4 SDRs with it.
As i cannot do that directly i need a clock buffer in between.
I could not determine what TCXO is used there exactly so i have no datasheet.
So far i know the TCXO that is used operates with a frequency of 28.8MHz. (will do more investigations on the signal that is provided as soon as i get access to an oscilloscope).
So i made a small board (to sum it up) that contains one of the TCXOs and the clock buffer. The TCXO drives the clock buffer directly.
The 4 outputs of the clock buffer now are connected to coaxial cables each, that lead the clock buffer output signal to the SDR-sticks. (to the pin where the TCXO has been removed before)
I need the long cables cause i want to plug the 4 SDR-sticks into a computer later.

@Baluncore: The IC on the SDR that is then clocked with the distributed clock signal is this one (R820T):
http://superkuh.com/gnuradio/R820T_datasheet-Non_R-20111130_unlocked.pdf

I need to use the oscillator that i have previously removed from the SDR so I am thinking about options i have now.

@berkeman: I hope i could provide some information regarding your questions. Also i decided to use 33ohm terminating resistors as it is suggested in the datasheet of the buffer (for most buffers actually) in case the trace after the output is longer than 1inch, what obviously is the case for me ;)

@lewando: So you say using the IDT part could work in case i add a DC block in between the TCXO and the clock buffer? The chip that will be driven with the clock signal in the end is this one posted above, the R820T: http://superkuh.com/gnuradio/R820T_datasheet-Non_R-20111130_unlocked.pdf
On page 23 in the datasheet of the R820T posted above:

Input level to XTAL_in pin when using external cloc: min 120 mVp-p | max: 3300 mVp-p

So would i need a level shift in this case? As the chip seems to be able to handle pretty "low" signals.
What exactly do you mean by "biasing the clock on the IDT side with VDD/2"?

Does it matter what kind of signal the R820T gets in the end (clipped sinewave, sinewave, square wave)?

Right now I am quite confused, maybe after i have posted some more info now one of you guys can make things a bit clearer for me.
I now see that the problem seems to be that currently the clock signal provided by the TCXO is too low for the buffer to detect a "HIGH".
So theoretically it should be possible to get this working by picking anohter clock buffer that can detect a "HIGH" at a lower level?

thank you so much, all of you for all the great imput!

 

[Baluncore]

The IC on the SDR that is then clocked with the distributed clock signal is this one (R820T):

On page 7 of the R820T2 preliminary data sheet is shown a simplified functional block diagram of the synthesiser. It is clear that you will be unable to synchronise the phase of the first local oscillators, all you can do is lock the frequencies by using the same reference clock signal. Unfortunately Rafael Microelectronics will not publicly release the full data sheet for the R820T.

You have not explained the reason why you need to tie the channels together on the same frequency.
1. Is it because you want some phase relationship between the IF outputs of different channels ?
2. Or is it to keep the LO1 interference out of the parallel channels ?

 

[lewando]

@lewando: So you say using the IDT part could work in case i add a DC block in between the TCXO and the clock buffer?

Yes, that is what I am saying. DC block and bias network.

The chip that will be driven with the clock signal in the end is this one posted above, the R820T: http://superkuh.com/gnuradio/R820T_datasheet-Non_R-20111130_unlocked.pdf
On page 23 in the datasheet of the R820T posted above:
Input level to XTAL_in pin when using external cloc: min 120 mVp-p | max: 3300 mVp-p
So would i need a level shift in this case? As the chip seems to be able to handle pretty "low" signals.

No. If you are powering the IDT part with 1.2 V it will provide a clock with roughly 1200 mVp-p. Which is within the datasheet's spec.

What exactly do you mean by "biasing the clock on the IDT side with VDD/2"?

Something like this:

Does it matter what kind of signal the R820T gets in the end (clipped sinewave, sinewave, square wave)?

Seems to already be happy with the clipped sinewave (with the TCXO in close proximity) The "square wave" (nothing is going to actually be "square" ) coming out of the remote IDT part would be fine (provided you don't ignore @berkeman 's point about termination).

Right now I am quite confused, maybe after i have posted some more info now one of you guys can make things a bit clearer for me.
I now see that the problem seems to be that currently the clock signal provided by the TCXO is too low for the buffer to detect a "HIGH".
So theoretically it should be possible to get this working by picking anohter clock buffer that can detect a "HIGH" at a lower level?

The thing is, we don't know much about the clipped sinewave waveform other than it has a minimum signal level of 0.8 Vp-p. You want to make sure the signal appears right in the middle of the buffer's CMOS input voltage spec range.

 

[lewando]

Some loose ends:

post #1:

Could i drive it with the following oscillator?
http://www.taitien.com/wp-content/uploads/2015/12/XO-0084_TW_TYPE_TCXO.pdf

Realize that this is a datasheet for a family of TCXOs, not a specific device.

post # 3:

The oscillator should provide a clipped sinewave output signal.

Is this is a guess based on the probability of it being so? You should want to know this with certainty.

post #5:

Because right now the oscillator seems to work but the clock buffer shows no reaction at the outputs.

How have you determined that "the oscillator seems to work"?

 

[Tom48]

Once again a big thank you to all of you for all the input!

@Baluncore: I would like to tie the channels because i want to experiment with angle of arrival estimation.
@lewando: As i said, i did not yet have access to an oscilloscope (but soon) that's why some of my statements regarding the oscillator signal are a bit vague.Another thing that is not clear to me at the moment:
If we check the datasheet of the R820T (page 23): http://superkuh.com/gnuradio/R820T_datasheet-Non_R-20111130_unlocked.pdf

We can see the in table 6-1: Input level to XTAL_in pin when using external cloc: min 120 mVp-p | max: 3300 mVp-p.

This tells me that the signal that is expected should be in between the range 120mV and 3300mV peak to peak.
But it doesn't tell me what levels are required for the two states to be detected properly (level p-p to detect a 'HIGH' and level p-p to detect a 'LOW').
Or does that not matter for this specific signal at the clock input of the R820T?

If we check the datasheet of the IDT buffer (page 4, first table for VDD=1.2 V): http://www.idt.com/document/621-datasheet

It would output 0.75VDD (= 0.9V) min for a 'HIGH' and 0.25VDD (= 0.3V) max for a 'LOW'.
How do i know that is ok for the R820T?

Also if i meassure the signal provided by the oscillator, this signal must be at least 0.65VDD (= 0.78V) peak to peak (=from negative wave bottom to positive wave top), so the IDT buffer can detect the signal at its inputs, is that right?Thank you so much, i really appreciate all your help! :)

 

[lewando]

We can see the in table 6-1: Input level to XTAL_in pin when using external cloc: min 120 mVp-p | max: 3300 mVp-p.
This tells me that the signal that is expected should be in between the range 120mV and 3300mV peak to peak.
But it doesn't tell me what levels are required for the two states to be detected properly (level p-p to detect a 'HIGH' and level p-p to detect a 'LOW').
Or does that not matter for this specific signal at the clock input of the R820T?

You are right, it does not matter. This input is likely AC-coupled internally (with internal bias network), as inferred by the "p-p" spec formulation.

It would output 0.75VDD (= 0.9V) min for a 'HIGH' and 0.25VDD (= 0.3V) max for a 'LOW'.
How do i know that is ok for the R820T?

(0.9 V - 0.3 V) = 0.6 V = 600 mVp-p. Within spec of the R820T.

Also if i meassure the signal provided by the oscillator, this signal must be at least 0.65VDD (= 0.78V) peak to peak (=from negative wave bottom to positive wave top), so the IDT buffer can detect the signal at its inputs, is that right?

(0.65 * 1.2 V) - (0.35 * 1.2 V) = 0.54 V "window". The TCXO is outputing something greater than 0.8 V. So you should be good.

 

[Baluncore]

I would like to tie the channels because i want to experiment with angle of arrival estimation.

I believe that angle of arrival would need to measure the phase difference of the received signals. Unfortunately the phase difference requires the first local oscillators of the multiple antenna receive channels be phase locked. That is not possible with the LO1 provided in that downconverter.

If you look at the functional block diagram you will see that LO1 to the mixer is supplied from a VCO through a divider. That makes me think the mixer is an image rejection IQ mixer. The synthesiser that generates the VCO control voltage through CP, has a programmable frequency divider, PFD, on the reference crystal frequency, being phase locked to a prescaler-divider, Div of the VCO.

There is no way you can predict the phase of the LO1 since the VCOs will start up at different times and the dividers will start with different initial values. You will then program them at different times and they will take different times to lock. That means you cannot simply use IF phase to detect RF carrier phase differences.

If you can lock the frequency of all reference oscillators, then you might consider a reference signal that can be injected into all RF channels. You can then measure the phase of those IF signals to calculate the phase error of each channel. If it was strong enough, one incoming signal could be fed to all channels and be used as a phase calibration signal.

Another possibility would be to swap antennas between receive channels, the LO1 phase differences that are measured in the IF could then be cancelled.

I'm sorry it is not good news, I want 16 channels of phase locked first local oscillators for a similar application. The R820T might have done the job if we had access to the internal LO.

 

[Baluncore]

To see the internal Xtal reference clock you may need to enable the clock output.
That appears to be bit 4 of register 15. See attached register descriptions.pdf