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Need help in understand the Markers on electronic chips

  1. Jan 9, 2014 #1
    Need help in understand the "Markers" on electronic chips

    [​IMG]

    I am just wondering what is the markers telling us, like what has shown in the diagram, the CLR is telling us if we apply active-high state input to that port, the flip flop will be reset right? But there is some case where the Markers is labeled as CLR' (bar-CLR) and there is a bubble attached at the port it should be something like "NOT gate". So in this case how do i determine whether should i apply high or low state to reset my flip flop?

    If CLR is labeled without bar, does it mean when the port receive high state, ff is reset;
    and if CLR is labeled with bar, does it mean when the port receive low state, ff is reset?

    Do the bubble determine anything?
     
  2. jcsd
  3. Jan 10, 2014 #2
    [​IMG]

    This is the type of flip flop i see in my note, if the CLR port is active-Low, so supplying high state into the port will get inverted by the bubble b4 the port then become low, so can i say the flip flop is reset in this configuration?


    But my note keep using this kind of configuration to avoid the flip flop from getting reset...
     
    Last edited: Jan 10, 2014
  4. Jan 10, 2014 #3

    berkeman

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    Staff: Mentor

    No, the bubble is a marker, not an active thing. The bubble indicates active low for inputs, so the CLR~ input clears the FF when it is driven low. And the bubble and > markings on the clock input indicate that the clock causes the data to propagate on the negative-going edge of the clock input.
     
    Last edited: Jan 10, 2014
  5. Jan 10, 2014 #4
    oh, is that mean there is no such things like a CLR~ without bubble marker?
     
  6. Jan 10, 2014 #5

    berkeman

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    Staff: Mentor

    Correct. No bubble means you use the active high signal CLR. A bubble means that the active low signal CLR~ is used to clear the FF. :smile:
     
  7. Jan 10, 2014 #6
    Ah I see, thank you very much :)
     
  8. Jan 10, 2014 #7
    Take a look at this, which explains a little about why designers use certain symbols:
    http://www.eetimes.com/document.asp?doc_id=1274541

    This page also explains some of it about halfway down, under "DeMorgan's Theorem":
    http://www.physics.mcmaster.ca/phys4db3/Lab/chapter5.htm

    Also
    http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/gate.html#c2

    and this slide show isn't bad
    http://webdocs.cs.ualberta.ca/~amaral/courses/329/webslides/Topic8-DocTimeDiagrams/sld011.htm

    I couldn't find any pages that do a fantastic job of explaining this...
     
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